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e17b1af96b
The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: <stable@vger.kernel.org> # v4.9+ Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> |
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| .. | ||
| .gitignore | ||
| atags_to_fdt.c | ||
| big-endian.S | ||
| debug.S | ||
| decompress.c | ||
| efi-header.S | ||
| head-sa1100.S | ||
| head-sharpsl.S | ||
| head-xscale.S | ||
| head.S | ||
| libfdt_env.h | ||
| ll_char_wr.S | ||
| Makefile | ||
| misc.c | ||
| misc.h | ||
| piggy.S | ||
| string.c | ||
| vmlinux.lds.S | ||