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8a329dbd4a
The TLV320ADCx140 parts support Dynamic Range Enhancer (DRE) as defined in Section 8.3.2 of the data sheets. The DRE achieves a complete-channel dynamic range as high as 120 dB. At a system level, the DRE scheme enables far-field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud environments. There are 2 enables for DRE. The first is a global setting that enables the DRE engine in the device and the other enable is per channel. If the DRE is enabled globally then either DRE or AGC can be used per each configured channel. If global DRE is disabled then even setting the DRE enable bit in the channel config register will have no effect. Signed-off-by: Dan Murphy <dmurphy@ti.com> Link: https://lore.kernel.org/r/20200221181358.22526-1-dmurphy@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// TLV320ADCX104 Sound driver
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// Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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#ifndef _TLV320ADCX140_H
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#define _TLV320ADCX140_H
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#define ADCX140_RATES (SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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#define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define ADCX140_PAGE_SELECT 0x00
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#define ADCX140_SW_RESET 0x01
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#define ADCX140_SLEEP_CFG 0x02
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#define ADCX140_SHDN_CFG 0x05
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#define ADCX140_ASI_CFG0 0x07
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#define ADCX140_ASI_CFG1 0x08
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#define ADCX140_ASI_CFG2 0x09
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#define ADCX140_ASI_CH1 0x0b
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#define ADCX140_ASI_CH2 0x0c
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#define ADCX140_ASI_CH3 0x0d
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#define ADCX140_ASI_CH4 0x0e
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#define ADCX140_ASI_CH5 0x0f
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#define ADCX140_ASI_CH6 0x10
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#define ADCX140_ASI_CH7 0x11
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#define ADCX140_ASI_CH8 0x12
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#define ADCX140_MST_CFG0 0x13
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#define ADCX140_MST_CFG1 0x14
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#define ADCX140_ASI_STS 0x15
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#define ADCX140_CLK_SRC 0x16
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#define ADCX140_PDMCLK_CFG 0x1f
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#define ADCX140_PDM_CFG 0x20
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#define ADCX140_GPIO_CFG0 0x21
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#define ADCX140_GPO_CFG1 0x22
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#define ADCX140_GPO_CFG2 0x23
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#define ADCX140_GPO_CFG3 0x24
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#define ADCX140_GPO_CFG4 0x25
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#define ADCX140_GPO_VAL 0x29
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#define ADCX140_GPIO_MON 0x2a
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#define ADCX140_GPI_CFG0 0x2b
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#define ADCX140_GPI_CFG1 0x2c
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#define ADCX140_GPI_MON 0x2f
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#define ADCX140_INT_CFG 0x32
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#define ADCX140_INT_MASK0 0x33
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#define ADCX140_INT_LTCH0 0x36
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#define ADCX140_BIAS_CFG 0x3b
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#define ADCX140_CH1_CFG0 0x3c
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#define ADCX140_CH1_CFG1 0x3d
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#define ADCX140_CH1_CFG2 0x3e
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#define ADCX140_CH1_CFG3 0x3f
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#define ADCX140_CH1_CFG4 0x40
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#define ADCX140_CH2_CFG0 0x41
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#define ADCX140_CH2_CFG1 0x42
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#define ADCX140_CH2_CFG2 0x43
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#define ADCX140_CH2_CFG3 0x44
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#define ADCX140_CH2_CFG4 0x45
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#define ADCX140_CH3_CFG0 0x46
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#define ADCX140_CH3_CFG1 0x47
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#define ADCX140_CH3_CFG2 0x48
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#define ADCX140_CH3_CFG3 0x49
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#define ADCX140_CH3_CFG4 0x4a
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#define ADCX140_CH4_CFG0 0x4b
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#define ADCX140_CH4_CFG1 0x4c
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#define ADCX140_CH4_CFG2 0x4d
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#define ADCX140_CH4_CFG3 0x4e
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#define ADCX140_CH4_CFG4 0x4f
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#define ADCX140_CH5_CFG2 0x52
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#define ADCX140_CH5_CFG3 0x53
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#define ADCX140_CH5_CFG4 0x54
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#define ADCX140_CH6_CFG2 0x57
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#define ADCX140_CH6_CFG3 0x58
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#define ADCX140_CH6_CFG4 0x59
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#define ADCX140_CH7_CFG2 0x5c
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#define ADCX140_CH7_CFG3 0x5d
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#define ADCX140_CH7_CFG4 0x5e
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#define ADCX140_CH8_CFG2 0x61
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#define ADCX140_CH8_CFG3 0x62
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#define ADCX140_CH8_CFG4 0x63
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#define ADCX140_DSP_CFG0 0x6b
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#define ADCX140_DSP_CFG1 0x6c
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#define ADCX140_DRE_CFG0 0x6d
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#define ADCX140_AGC_CFG0 0x70
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#define ADCX140_IN_CH_EN 0x73
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#define ADCX140_ASI_OUT_CH_EN 0x74
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#define ADCX140_PWR_CFG 0x75
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#define ADCX140_DEV_STS0 0x76
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#define ADCX140_DEV_STS1 0x77
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#define ADCX140_RESET BIT(0)
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#define ADCX140_WAKE_DEV BIT(0)
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#define ADCX140_AREG_INTERNAL BIT(7)
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#define ADCX140_BCLKINV_BIT BIT(2)
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#define ADCX140_FSYNCINV_BIT BIT(3)
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#define ADCX140_INV_MSK (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT)
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#define ADCX140_BCLK_FSYNC_MASTER BIT(7)
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#define ADCX140_I2S_MODE_BIT BIT(6)
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#define ADCX140_LEFT_JUST_BIT BIT(7)
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#define ADCX140_ASI_FORMAT_MSK (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT)
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#define ADCX140_16_BIT_WORD 0x0
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#define ADCX140_20_BIT_WORD BIT(4)
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#define ADCX140_24_BIT_WORD BIT(5)
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#define ADCX140_32_BIT_WORD (BIT(4) | BIT(5))
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#define ADCX140_WORD_LEN_MSK 0x30
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#define ADCX140_MAX_CHANNELS 8
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#define ADCX140_MIC_BIAS_VAL_VREF 0
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#define ADCX140_MIC_BIAS_VAL_VREF_1096 1
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#define ADCX140_MIC_BIAS_VAL_AVDD 6
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#define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4)
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#define ADCX140_MIC_BIAS_VREF_275V 0
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#define ADCX140_MIC_BIAS_VREF_25V 1
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#define ADCX140_MIC_BIAS_VREF_1375V 2
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#define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0)
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#define ADCX140_PWR_CFG_BIAS_PDZ BIT(7)
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#define ADCX140_PWR_CFG_ADC_PDZ BIT(6)
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#define ADCX140_PWR_CFG_PLL_PDZ BIT(5)
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#define ADCX140_TX_OFFSET_MASK GENMASK(4, 0)
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#endif /* _TLV320ADCX140_ */
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