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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 19:06:41 +07:00
aef11009c4
This patch adds four new IOCTLs to amdkfd. These IOCTLs expose a H/W debugger functionality to the userspace. The IOCTLs are: - AMDKFD_IOC_DBG_REGISTER: The purpose of this IOCTL is to notify amdkfd that a process wants to use GPU debugging facilities on itself only. It is expected that this IOCTL would be called before any other H/W debugger requests are sent to amdkfd and for each GPU where the H/W debugging needs to be enabled. The use of this IOCTL ensures that only one instance of a debugger is active in the system. - AMDKFD_IOC_DBG_UNREGISTER: This IOCTL detaches the debugger/debugged process from the H/W Debug which was established by the AMDKFD_IOC_DBG_REGISTER IOCTL. - AMDKFD_IOC_DBG_ADDRESS_WATCH: This IOCTL allows to set different watchpoints with various conditions as indicated by the IOCTL's arguments. The available number of watchpoints is retrieved from topology. This operation is confined to the current debugged process, which was registered through AMDKFD_IOC_DBG_REGISTER. - AMDKFD_IOC_DBG_WAVE_CONTROL: This IOCTL allows to control a wavefront as indicated by the IOCTL's arguments. For example, you can halt/resume or kill either a single wavefront or a set of wavefronts. This operation is confined to the current debugged process, which was registered through AMDKFD_IOC_DBG_REGISTER. Because the arguments for the address watch IOCTL and wave control IOCTL are dynamic, meaning that they could vary in size, the userspace passes a pointer to a structure (in userspace) that contains the value of the arguments. The kernel driver is responsible to parse this structure and validate its contents. v2: change void* to uint64_t inside ioctl arguments Signed-off-by: Yair Shachar <yair.shachar@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
293 lines
8.6 KiB
C
293 lines
8.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef KFD_IOCTL_H_INCLUDED
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#define KFD_IOCTL_H_INCLUDED
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define KFD_IOCTL_MAJOR_VERSION 1
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#define KFD_IOCTL_MINOR_VERSION 1
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struct kfd_ioctl_get_version_args {
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uint32_t major_version; /* from KFD */
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uint32_t minor_version; /* from KFD */
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};
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/* For kfd_ioctl_create_queue_args.queue_type. */
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#define KFD_IOC_QUEUE_TYPE_COMPUTE 0
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#define KFD_IOC_QUEUE_TYPE_SDMA 1
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#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
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#define KFD_MAX_QUEUE_PERCENTAGE 100
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#define KFD_MAX_QUEUE_PRIORITY 15
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struct kfd_ioctl_create_queue_args {
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uint64_t ring_base_address; /* to KFD */
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uint64_t write_pointer_address; /* from KFD */
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uint64_t read_pointer_address; /* from KFD */
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uint64_t doorbell_offset; /* from KFD */
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uint32_t ring_size; /* to KFD */
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uint32_t gpu_id; /* to KFD */
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uint32_t queue_type; /* to KFD */
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uint32_t queue_percentage; /* to KFD */
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uint32_t queue_priority; /* to KFD */
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uint32_t queue_id; /* from KFD */
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uint64_t eop_buffer_address; /* to KFD */
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uint64_t eop_buffer_size; /* to KFD */
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uint64_t ctx_save_restore_address; /* to KFD */
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uint64_t ctx_save_restore_size; /* to KFD */
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};
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struct kfd_ioctl_destroy_queue_args {
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uint32_t queue_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_update_queue_args {
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uint64_t ring_base_address; /* to KFD */
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uint32_t queue_id; /* to KFD */
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uint32_t ring_size; /* to KFD */
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uint32_t queue_percentage; /* to KFD */
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uint32_t queue_priority; /* to KFD */
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};
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/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
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#define KFD_IOC_CACHE_POLICY_COHERENT 0
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#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
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struct kfd_ioctl_set_memory_policy_args {
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uint64_t alternate_aperture_base; /* to KFD */
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uint64_t alternate_aperture_size; /* to KFD */
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uint32_t gpu_id; /* to KFD */
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uint32_t default_policy; /* to KFD */
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uint32_t alternate_policy; /* to KFD */
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uint32_t pad;
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};
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/*
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* All counters are monotonic. They are used for profiling of compute jobs.
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* The profiling is done by userspace.
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*
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* In case of GPU reset, the counter should not be affected.
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*/
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struct kfd_ioctl_get_clock_counters_args {
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uint64_t gpu_clock_counter; /* from KFD */
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uint64_t cpu_clock_counter; /* from KFD */
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uint64_t system_clock_counter; /* from KFD */
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uint64_t system_clock_freq; /* from KFD */
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uint32_t gpu_id; /* to KFD */
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uint32_t pad;
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};
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#define NUM_OF_SUPPORTED_GPUS 7
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struct kfd_process_device_apertures {
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uint64_t lds_base; /* from KFD */
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uint64_t lds_limit; /* from KFD */
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uint64_t scratch_base; /* from KFD */
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uint64_t scratch_limit; /* from KFD */
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uint64_t gpuvm_base; /* from KFD */
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uint64_t gpuvm_limit; /* from KFD */
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uint32_t gpu_id; /* from KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_get_process_apertures_args {
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struct kfd_process_device_apertures
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process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
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/* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
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uint32_t num_of_nodes;
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uint32_t pad;
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};
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#define MAX_ALLOWED_NUM_POINTS 100
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#define MAX_ALLOWED_AW_BUFF_SIZE 4096
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#define MAX_ALLOWED_WAC_BUFF_SIZE 128
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struct kfd_ioctl_dbg_register_args {
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uint32_t gpu_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_dbg_unregister_args {
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uint32_t gpu_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_dbg_address_watch_args {
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uint64_t content_ptr; /* a pointer to the actual content */
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uint32_t gpu_id; /* to KFD */
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uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
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};
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struct kfd_ioctl_dbg_wave_control_args {
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uint64_t content_ptr; /* a pointer to the actual content */
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uint32_t gpu_id; /* to KFD */
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uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
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};
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/* Matching HSA_EVENTTYPE */
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#define KFD_IOC_EVENT_SIGNAL 0
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#define KFD_IOC_EVENT_NODECHANGE 1
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#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
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#define KFD_IOC_EVENT_HW_EXCEPTION 3
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#define KFD_IOC_EVENT_SYSTEM_EVENT 4
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#define KFD_IOC_EVENT_DEBUG_EVENT 5
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#define KFD_IOC_EVENT_PROFILE_EVENT 6
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#define KFD_IOC_EVENT_QUEUE_EVENT 7
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#define KFD_IOC_EVENT_MEMORY 8
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#define KFD_IOC_WAIT_RESULT_COMPLETE 0
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#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
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#define KFD_IOC_WAIT_RESULT_FAIL 2
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#define KFD_SIGNAL_EVENT_LIMIT 256
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struct kfd_ioctl_create_event_args {
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uint64_t event_page_offset; /* from KFD */
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uint32_t event_trigger_data; /* from KFD - signal events only */
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uint32_t event_type; /* to KFD */
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uint32_t auto_reset; /* to KFD */
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uint32_t node_id; /* to KFD - only valid for certain
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event types */
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uint32_t event_id; /* from KFD */
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uint32_t event_slot_index; /* from KFD */
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};
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struct kfd_ioctl_destroy_event_args {
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uint32_t event_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_set_event_args {
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uint32_t event_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_reset_event_args {
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uint32_t event_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_memory_exception_failure {
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uint32_t NotPresent; /* Page not present or supervisor privilege */
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uint32_t ReadOnly; /* Write access to a read-only page */
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uint32_t NoExecute; /* Execute access to a page marked NX */
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uint32_t pad;
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};
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/* memory exception data*/
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struct kfd_hsa_memory_exception_data {
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struct kfd_memory_exception_failure failure;
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uint64_t va;
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uint32_t gpu_id;
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uint32_t pad;
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};
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/* Event data*/
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struct kfd_event_data {
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union {
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struct kfd_hsa_memory_exception_data memory_exception_data;
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}; /* From KFD */
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uint64_t kfd_event_data_ext; /* pointer to an extension structure
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for future exception types */
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uint32_t event_id; /* to KFD */
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uint32_t pad;
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};
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struct kfd_ioctl_wait_events_args {
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uint64_t events_ptr; /* pointed to struct
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kfd_event_data array, to KFD */
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uint32_t num_events; /* to KFD */
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uint32_t wait_for_all; /* to KFD */
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uint32_t timeout; /* to KFD */
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uint32_t wait_result; /* from KFD */
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};
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#define AMDKFD_IOCTL_BASE 'K'
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#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
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#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
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#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
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#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
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#define AMDKFD_IOC_GET_VERSION \
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AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
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#define AMDKFD_IOC_CREATE_QUEUE \
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AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
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#define AMDKFD_IOC_DESTROY_QUEUE \
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AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
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#define AMDKFD_IOC_SET_MEMORY_POLICY \
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AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
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#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
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AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
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#define AMDKFD_IOC_GET_PROCESS_APERTURES \
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AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
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#define AMDKFD_IOC_UPDATE_QUEUE \
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AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
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#define AMDKFD_IOC_CREATE_EVENT \
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AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
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#define AMDKFD_IOC_DESTROY_EVENT \
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AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
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#define AMDKFD_IOC_SET_EVENT \
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AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
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#define AMDKFD_IOC_RESET_EVENT \
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AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
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#define AMDKFD_IOC_WAIT_EVENTS \
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AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
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#define AMDKFD_IOC_DBG_REGISTER \
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AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
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#define AMDKFD_IOC_DBG_UNREGISTER \
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AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
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#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
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AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
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#define AMDKFD_IOC_DBG_WAVE_CONTROL \
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AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
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#define AMDKFD_COMMAND_START 0x01
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#define AMDKFD_COMMAND_END 0x11
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#endif
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