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9ca9737444
PREPARE_[DELAYED_]WORK() are being phased out. They have few users and a nasty surprise in terms of reentrancy guarantee as workqueue considers work items to be different if they don't have the same work function. nvme_dev->reset_work is multiplexed with multiple work functions. Introduce nvme_reset_workfn() which invokes nvme_dev->reset_workfn and always use it as the work function and update the users to set the ->reset_workfn field instead of overriding the work function using PREPARE_WORK(). It would probably be best to route this with other related updates through the workqueue tree. Compile tested. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: linux-nvme@lists.infradead.org
176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/*
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* Definitions for the NVM Express interface
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* Copyright (c) 2011-2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _LINUX_NVME_H
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#define _LINUX_NVME_H
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#include <uapi/linux/nvme.h>
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#include <linux/pci.h>
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#include <linux/miscdevice.h>
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#include <linux/kref.h>
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struct nvme_bar {
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__u64 cap; /* Controller Capabilities */
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__u32 vs; /* Version */
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__u32 intms; /* Interrupt Mask Set */
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__u32 intmc; /* Interrupt Mask Clear */
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__u32 cc; /* Controller Configuration */
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__u32 rsvd1; /* Reserved */
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__u32 csts; /* Controller Status */
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__u32 rsvd2; /* Reserved */
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__u32 aqa; /* Admin Queue Attributes */
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__u64 asq; /* Admin SQ Base Address */
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__u64 acq; /* Admin CQ Base Address */
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};
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#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
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#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
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#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
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#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
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enum {
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NVME_CC_ENABLE = 1 << 0,
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NVME_CC_CSS_NVM = 0 << 4,
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NVME_CC_MPS_SHIFT = 7,
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NVME_CC_ARB_RR = 0 << 11,
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NVME_CC_ARB_WRRU = 1 << 11,
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NVME_CC_ARB_VS = 7 << 11,
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NVME_CC_SHN_NONE = 0 << 14,
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NVME_CC_SHN_NORMAL = 1 << 14,
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NVME_CC_SHN_ABRUPT = 2 << 14,
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NVME_CC_SHN_MASK = 3 << 14,
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NVME_CC_IOSQES = 6 << 16,
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NVME_CC_IOCQES = 4 << 20,
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NVME_CSTS_RDY = 1 << 0,
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NVME_CSTS_CFS = 1 << 1,
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NVME_CSTS_SHST_NORMAL = 0 << 2,
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NVME_CSTS_SHST_OCCUR = 1 << 2,
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NVME_CSTS_SHST_CMPLT = 2 << 2,
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NVME_CSTS_SHST_MASK = 3 << 2,
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};
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#define NVME_VS(major, minor) (major << 16 | minor)
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#define NVME_IO_TIMEOUT (5 * HZ)
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/*
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* Represents an NVM Express device. Each nvme_dev is a PCI function.
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*/
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struct nvme_dev {
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struct list_head node;
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struct nvme_queue **queues;
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u32 __iomem *dbs;
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struct pci_dev *pci_dev;
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struct dma_pool *prp_page_pool;
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struct dma_pool *prp_small_pool;
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int instance;
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int queue_count;
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u32 db_stride;
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u32 ctrl_config;
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struct msix_entry *entry;
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struct nvme_bar __iomem *bar;
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struct list_head namespaces;
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struct kref kref;
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struct miscdevice miscdev;
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work_func_t reset_workfn;
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struct work_struct reset_work;
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char name[12];
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char serial[20];
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char model[40];
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char firmware_rev[8];
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u32 max_hw_sectors;
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u32 stripe_size;
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u16 oncs;
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u16 abort_limit;
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u8 initialized;
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};
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/*
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* An NVM Express namespace is equivalent to a SCSI LUN
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*/
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struct nvme_ns {
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struct list_head list;
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struct nvme_dev *dev;
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struct request_queue *queue;
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struct gendisk *disk;
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unsigned ns_id;
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int lba_shift;
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int ms;
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u64 mode_select_num_blocks;
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u32 mode_select_block_len;
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};
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/*
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* The nvme_iod describes the data in an I/O, including the list of PRP
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* entries. You can't see it in this data structure because C doesn't let
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* me express that. Use nvme_alloc_iod to ensure there's enough space
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* allocated to store the PRP list.
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*/
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struct nvme_iod {
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void *private; /* For the use of the submitter of the I/O */
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int npages; /* In the PRP list. 0 means small pool in use */
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int offset; /* Of PRP list */
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int nents; /* Used in scatterlist */
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int length; /* Of data, in bytes */
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unsigned long start_time;
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dma_addr_t first_dma;
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struct scatterlist sg[0];
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};
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static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
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{
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return (sector >> (ns->lba_shift - 9));
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}
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/**
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* nvme_free_iod - frees an nvme_iod
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* @dev: The device that the I/O was submitted to
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* @iod: The memory to free
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*/
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void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);
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int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
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struct nvme_iod *iod, int total_len, gfp_t gfp);
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struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
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unsigned long addr, unsigned length);
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void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
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struct nvme_iod *iod);
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struct nvme_queue *get_nvmeq(struct nvme_dev *dev);
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void put_nvmeq(struct nvme_queue *nvmeq);
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int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
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u32 *result, unsigned timeout);
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int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns);
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int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
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u32 *result);
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int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
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dma_addr_t dma_addr);
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int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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dma_addr_t dma_addr, u32 *result);
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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dma_addr_t dma_addr, u32 *result);
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struct sg_io_hdr;
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int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
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int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
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int nvme_sg_get_version_num(int __user *ip);
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#endif /* _LINUX_NVME_H */
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