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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bd7aff0340
It is a bit unorthodox to just include a file in the middle of a another DTS file, it breaks the pattern from other device trees and also makes it really hard to reference things across the files with phandles. Restructure the include for the Versatile Express motherboards to happen at the top of the file, reference the target nodes directly, and indent the motherboard .dtsi files to reflect their actual depth in the hierarchy. This is a purely syntactic change that result in the same DTB files from the DTS/DTSI files. Cc: Robin Murphy <robin.murphy@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
192 lines
5.3 KiB
Plaintext
192 lines
5.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* LogicTile Express 20MG
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* V2F-1XV7
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*
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* Cortex-A53 (2 cores) Soft Macrocell Model
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*
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* HBI-0247C
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "vexpress-v2m-rs1.dtsi"
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/ {
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model = "V2F-1XV7 Cortex-A53x2 SMM";
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arm,hbi = <0x247>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = "serial0:38400n8";
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};
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0>;
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next-level-cache = <&L2_0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 1>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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smbclk: smclk {
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/* SMC clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 4>;
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freq-range = <40000000 40000000>;
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#clock-cells = <0>;
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clock-output-names = "smclk";
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};
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volt-vio {
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/* VIO to expansion board above */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VIO_UP";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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volt-12v {
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/* 12V from power connector J6 */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 1>;
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regulator-name = "12";
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regulator-always-on;
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};
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temp-fpga {
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/* FPGA temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "FPGA";
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};
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};
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smb: smb@8000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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