José Roberto de Souza 4ab4fa1032 drm/i915/psr: Make PSR registers relative to transcoders ... PSR registers are a mess, some have the full address while others just have the additional offset from psr_mmio_base. For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and using it makes more difficult for people with an PSR register address or PSR register name from from BSpec as i915 also don't match the BSpec names. For HSW psr_mmio_base is _DDI_BUF_CTL_A + 0x800 and PSR registers are only available in DDIA. Other reason to make relative to transcoder is that since BDW every transcoder have PSR registers, so in theory it should be possible to have PSR enabled in a non-eDP transcoder. So for BDW+ we can use _TRANS2() to get the register offset of any PSR register in any transcoder while for HSW we have _HSW_PSR_ADJ that will calculate the register offset for the single PSR instance, noting that we are already guarded about trying to enable PSR in other port than DDIA on HSW by the 'if (dig_port->base.port != PORT_A)' in intel_psr_compute_config(), this check should only be valid for HSW and will be changed in future. PSR2 registers and PSR_EVENT was added after Haswell so that is why _PSR_ADJ() is not used in some macros. The only registers that can not be relative to transcoder are PSR_IMR and PSR_IIR that are not relative to anything, so keeping it hardcoded. That changed for TGL but it will be handled in another patch. Also removing BDW_EDP_PSR_BASE from GVT because it is not used as it is the only PSR register that GVT have. v5: - Macros changed to be more explicit about HSW (Dhinakaran) - Squashed with the patch that added the tran parameter to the macros (Dhinakaran) v6: - Checking for interruption errors after module reload in the transcoder that will be used (Dhinakaran) - Using lowercase to the registers offsets v7: - Removing IS_HASWELL() from registers macros(Jani) Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190820223325.27490-1-jose.souza@intel.com		2019-08-22 13:09:06 -07:00
..
aperture_gm.c	drm/i915: Track ggtt fence reservations under its own mutex	2019-08-22 08:53:40 +01:00
cfg_space.c
cmd_parser.c	Merge drm/drm-next into drm-intel-next-queued	2019-08-22 00:10:36 -07:00
cmd_parser.h
debug.h
debugfs.c	drm/i915/gvt: no need to check return value of debugfs_create functions	2019-08-13 17:55:06 +08:00
display.c
display.h
dmabuf.c
dmabuf.h
edid.c
edid.h
execlist.c
execlist.h
fb_decoder.c	drm/i915/gvt: Don't use ggtt_validdate_range() with size=0	2019-07-30 14:29:48 +08:00
fb_decoder.h
firmware.c
gtt.c	drm/i915/gvt: Warning for invalid ggtt access	2019-07-30 14:29:48 +08:00
gtt.h
gvt.c	drm/i915/gvt: no need to check return value of debugfs_create functions	2019-08-13 17:55:06 +08:00
gvt.h	drm/i915/gvt: factor out tlb and mocs register offset table	2019-08-13 17:55:06 +08:00
handlers.c	drm/i915/psr: Make PSR registers relative to transcoders	2019-08-22 13:09:06 -07:00
hypercall.h
interrupt.c	drm/i915/gvt: Fix typo of VBLANK_TIMER_PERIOD	2019-08-13 17:54:41 +08:00
interrupt.h
kvmgt.c	Merge drm/drm-next into drm-intel-next-queued	2019-08-22 00:10:36 -07:00
Makefile
mmio_context.c	drm/i915/gvt: factor out tlb and mocs register offset table	2019-08-13 17:55:06 +08:00
mmio_context.h
mmio.c
mmio.h
mpt.h
opregion.c
page_track.c
page_track.h
reg.h
sched_policy.c
sched_policy.h
scheduler.c	Merge drm/drm-next into drm-intel-next-queued	2019-08-22 00:10:36 -07:00
scheduler.h
trace_points.c	drm/i915/gvt: remove duplicate include of trace.h	2019-07-30 14:26:30 +08:00
trace.h
vgpu.c	drm/i915/gvt: no need to check return value of debugfs_create functions	2019-08-13 17:55:06 +08:00