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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f8a096059f
Use devm_ and pcim_ functions to make error handling simpler and code smaller and tidier. Based on original patch by mei: me: use managed functions pcim_* and devm_* https://lkml.org/lkml/2016/2/1/339 Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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*
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* Intel Management Engine Interface (Intel MEI) Linux driver
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* Copyright (c) 2013-2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef _MEI_HW_TXE_H_
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#define _MEI_HW_TXE_H_
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#include <linux/irqreturn.h>
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#include "hw.h"
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#include "hw-txe-regs.h"
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#define MEI_TXI_RPM_TIMEOUT 500 /* ms */
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/* Flatten Hierarchy interrupt cause */
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#define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */
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#define TXE_INTR_READINESS HISR_INT_0_STS
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#define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */
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#define TXE_INTR_ALIVENESS HISR_INT_1_STS
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#define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */
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#define TXE_INTR_OUT_DB HISR_INT_2_STS
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#define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */
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#define TXE_INTR_IN_READY BIT(8)
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/**
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* struct mei_txe_hw - txe hardware specifics
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*
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* @mem_addr: SeC and BRIDGE bars
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* @aliveness: aliveness (power gating) state of the hardware
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* @readiness: readiness state of the hardware
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* @slots: number of empty slots
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* @wait_aliveness_resp: aliveness wait queue
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* @intr_cause: translated interrupt cause
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*/
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struct mei_txe_hw {
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void __iomem * const *mem_addr;
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u32 aliveness;
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u32 readiness;
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u32 slots;
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wait_queue_head_t wait_aliveness_resp;
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unsigned long intr_cause;
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};
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#define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw)
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static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw)
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{
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return container_of((void *)hw, struct mei_device, hw);
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}
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struct mei_device *mei_txe_dev_init(struct pci_dev *pdev);
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irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id);
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irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id);
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int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req);
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int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range);
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#endif /* _MEI_HW_TXE_H_ */
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