mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 16:36:53 +07:00
54e269ead6
Patch from Deepak Saxena The expansion bus on the IXP46x NPU can be configured for either 32MiB or 16MiB windows and changing the configuration causes the base address for each chip select for each region to change. Because of this, we cannot hardcode the physical base as we currently do. This patch checks the expansion bus configuration registers at runtime to determine the appropriate window size. Note that this requires that the bootloader already configured the device sizes appropriately, but I feel that is valid assumption to make as the bootloader must configure and access the flash window, the output display (LCD, LEDs, etc) window, and other expansion bus devices. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
34 lines
942 B
C
34 lines
942 B
C
/*
|
|
* include/asm-arm/arch-ixp4xx/coyote.h
|
|
*
|
|
* ADI Engineering platform specific definitions
|
|
*
|
|
* Author: Deepak Saxena <dsaxena@plexity.net>
|
|
*
|
|
* Copyright 2004 (c) MontaVista, Software, Inc.
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_HARDWARE_H__
|
|
#error "Do not include this directly, instead #include <asm/hardware.h>"
|
|
#endif
|
|
|
|
/* PCI controller GPIO to IRQ pin mappings */
|
|
#define COYOTE_PCI_SLOT0_PIN 6
|
|
#define COYOTE_PCI_SLOT1_PIN 11
|
|
|
|
#define COYOTE_PCI_SLOT0_DEVID 14
|
|
#define COYOTE_PCI_SLOT1_DEVID 15
|
|
|
|
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
|
|
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
|
|
#define COYOTE_IDE_REGION_SIZE 0x1000
|
|
|
|
#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
|
|
#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
|
|
#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
|
|
|