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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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49b4ff3304
Spelling fixes in arch/cris/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Adrian Bunk <bunk@kernel.org>
157 lines
3.8 KiB
C
157 lines
3.8 KiB
C
/*
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* arch/cris/arch-v32/drivers/nandflash.c
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*
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* Copyright (c) 2004
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*
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* Derived from drivers/mtd/nand/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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*
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* $Id: nandflash.c,v 1.3 2005/06/01 10:57:12 starvik Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/arch/memmap.h>
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/gio_defs.h>
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#include <asm/arch/hwregs/bif_core_defs.h>
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#include <asm/io.h>
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#define CE_BIT 4
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#define CLE_BIT 5
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#define ALE_BIT 6
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#define BY_BIT 7
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static struct mtd_info *crisv32_mtd = NULL;
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/*
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* hardware specific access to control-lines
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*/
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static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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unsigned long flags;
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reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout);
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local_irq_save(flags);
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switch(cmd){
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case NAND_CTL_SETCLE:
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dout.data |= (1<<CLE_BIT);
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break;
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case NAND_CTL_CLRCLE:
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dout.data &= ~(1<<CLE_BIT);
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break;
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case NAND_CTL_SETALE:
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dout.data |= (1<<ALE_BIT);
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break;
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case NAND_CTL_CLRALE:
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dout.data &= ~(1<<ALE_BIT);
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break;
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case NAND_CTL_SETNCE:
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dout.data |= (1<<CE_BIT);
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break;
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case NAND_CTL_CLRNCE:
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dout.data &= ~(1<<CE_BIT);
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break;
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}
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REG_WR(gio, regi_gio, rw_pa_dout, dout);
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local_irq_restore(flags);
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}
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/*
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* read device ready pin
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*/
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int crisv32_device_ready(struct mtd_info *mtd)
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{
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reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
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return ((din.data & (1 << BY_BIT)) >> BY_BIT);
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}
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/*
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* Main initialization routine
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*/
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struct mtd_info* __init crisv32_nand_flash_probe (void)
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{
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void __iomem *read_cs;
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void __iomem *write_cs;
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reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
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reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
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struct nand_chip *this;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
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GFP_KERNEL);
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if (!crisv32_mtd) {
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printk ("Unable to allocate CRISv32 NAND MTD device structure.\n");
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err = -ENOMEM;
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return NULL;
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}
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read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
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write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
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if (!read_cs || !write_cs) {
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printk("CRISv32 NAND ioremap failed\n");
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err = -EIO;
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goto out_mtd;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *) (&crisv32_mtd[1]);
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pa_oe.oe |= 1 << CE_BIT;
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pa_oe.oe |= 1 << ALE_BIT;
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pa_oe.oe |= 1 << CLE_BIT;
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pa_oe.oe &= ~ (1 << BY_BIT);
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REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
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bif_cfg.gated_csp0 = regk_bif_core_rd;
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bif_cfg.gated_csp1 = regk_bif_core_wr;
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REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
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/* Initialize structures */
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memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
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memset((char *) this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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crisv32_mtd->priv = this;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = read_cs;
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this->IO_ADDR_W = write_cs;
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this->hwcontrol = crisv32_hwcontrol;
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this->dev_ready = crisv32_device_ready;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->eccmode = NAND_ECC_SOFT;
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/* Enable the following for a flash based bad block table */
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this->options = NAND_USE_FLASH_BBT;
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/* Scan to find existence of the device */
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if (nand_scan (crisv32_mtd, 1)) {
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err = -ENXIO;
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goto out_ior;
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}
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return crisv32_mtd;
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out_ior:
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iounmap((void *)read_cs);
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iounmap((void *)write_cs);
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out_mtd:
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kfree (crisv32_mtd);
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return NULL;
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}
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