Isabel Zhang 15add0c2fe drm/amd/display: Add initialitions for PLL2 clock source ... [Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-06 15:04:38 -05:00
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dcn21_hubbub.c	drm/amd/display: add detile buffer size for renoir	2019-10-17 16:28:45 -04:00
dcn21_hubbub.h	drm/amd/display: update dcn21 hubbub registers	2019-10-17 16:28:51 -04:00
dcn21_hubp.c	drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU	2020-02-06 15:04:38 -05:00
dcn21_hubp.h	drm/amd/display: update chroma viewport wa	2019-12-18 16:09:08 -05:00
dcn21_hwseq.c	drm/amd/display: add separate of private hwss functions	2019-12-05 16:26:46 -05:00
dcn21_hwseq.h	drm/amd/display: add separate of private hwss functions	2019-12-05 16:26:46 -05:00
dcn21_init.c	drm/amd/display: Added locking for atomic update stream and update planes	2020-02-06 15:04:37 -05:00
dcn21_init.h	drm/amd/display: cleanup of function pointer tables	2019-11-19 10:12:53 -05:00
dcn21_link_encoder.c	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED	2019-11-13 15:29:44 -05:00
dcn21_link_encoder.h	drm/amd/display: add missing dcn link encoder regs	2019-12-18 16:09:06 -05:00
dcn21_resource.c	drm/amd/display: Add initialitions for PLL2 clock source	2020-02-06 15:04:38 -05:00
dcn21_resource.h
Makefile	amdgpu: Enable initial DCN support on POWER	2019-12-18 16:09:05 -05:00