mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 18:56:55 +07:00
25c6f39607
Now that we have a driver for the DVP, let's add its DT node. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/e22222ca7f41b960e9bb1a31e0dd2de95b8c0cd1.1591867332.git-series.maxime@cerno.tech
953 lines
19 KiB
Plaintext
953 lines
19 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include "bcm283x.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/bcm2835-pm.h>
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/ {
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compatible = "brcm,bcm2711";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gicv2>;
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clk_108MHz: clk-108M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <108000000>;
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clock-output-names = "108MHz-clock";
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};
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soc {
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/*
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* Defined ranges:
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* Common BCM283x peripherals
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* BCM2711-specific peripherals
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* ARM-local peripherals
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*/
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ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
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<0x7c000000 0x0 0xfc000000 0x02000000>,
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<0x40000000 0x0 0xff800000 0x00800000>;
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/* Emulate a contiguous 30-bit address range for DMA */
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dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
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/*
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* This node is the provider for the enable-method for
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* bringing up secondary cores.
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*/
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local_intc: local_intc@40000000 {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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};
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gicv2: interrupt-controller@40041000 {
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interrupt-controller;
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#interrupt-cells = <3>;
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compatible = "arm,gic-400";
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reg = <0x40041000 0x1000>,
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<0x40042000 0x2000>,
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<0x40044000 0x2000>,
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<0x40046000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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avs_monitor: avs-monitor@7d5d2000 {
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compatible = "brcm,bcm2711-avs-monitor",
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"syscon", "simple-mfd";
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reg = <0x7d5d2000 0xf00>;
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thermal: thermal {
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compatible = "brcm,bcm2711-thermal";
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#thermal-sensor-cells = <0>;
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};
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};
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dma: dma@7e007000 {
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compatible = "brcm,bcm2835-dma";
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reg = <0x7e007000 0xb00>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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/* DMA lite 7 - 10 */
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma0",
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"dma1",
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"dma2",
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"dma3",
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"dma4",
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"dma5",
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"dma6",
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"dma7",
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"dma8",
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"dma9",
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"dma10";
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#dma-cells = <1>;
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brcm,dma-channel-mask = <0x07f5>;
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};
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pm: watchdog@7e100000 {
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compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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reg = <0x7e100000 0x114>,
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<0x7e00a000 0x24>,
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<0x7ec11000 0x20>;
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clocks = <&clocks BCM2835_CLOCK_V3D>,
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<&clocks BCM2835_CLOCK_PERI_IMAGE>,
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<&clocks BCM2835_CLOCK_H264>,
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<&clocks BCM2835_CLOCK_ISP>;
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clock-names = "v3d", "peri_image", "h264", "isp";
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system-power-controller;
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};
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rng@7e104000 {
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compatible = "brcm,bcm2711-rng200";
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reg = <0x7e104000 0x28>;
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};
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uart2: serial@7e201400 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7e201400 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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status = "disabled";
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};
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uart3: serial@7e201600 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7e201600 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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status = "disabled";
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};
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uart4: serial@7e201800 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7e201800 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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status = "disabled";
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};
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uart5: serial@7e201a00 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x7e201a00 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_UART>,
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<&clocks BCM2835_CLOCK_VPU>;
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clock-names = "uartclk", "apb_pclk";
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arm,primecell-periphid = <0x00241011>;
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status = "disabled";
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};
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spi3: spi@7e204600 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204600 0x0200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@7e204800 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204800 0x0200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@7e204a00 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204a00 0x0200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi6: spi@7e204c00 {
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compatible = "brcm,bcm2835-spi";
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reg = <0x7e204c00 0x0200>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@7e205600 {
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compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
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reg = <0x7e205600 0x200>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@7e205800 {
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compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
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reg = <0x7e205800 0x200>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@7e205a00 {
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compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
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reg = <0x7e205a00 0x200>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c6: i2c@7e205c00 {
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compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
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reg = <0x7e205c00 0x200>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2835_CLOCK_VPU>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm1: pwm@7e20c800 {
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compatible = "brcm,bcm2835-pwm";
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reg = <0x7e20c800 0x28>;
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clocks = <&clocks BCM2835_CLOCK_PWM>;
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assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
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assigned-clock-rates = <10000000>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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hvs@7e400000 {
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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dvp: clock@7ef00000 {
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compatible = "brcm,brcm2711-dvp";
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reg = <0x7ef00000 0x10>;
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clocks = <&clk_108MHz>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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/*
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* emmc2 has different DMA constraints based on SoC revisions. It was
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* moved into its own bus, so as for RPi4's firmware to update them.
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* The firmware will find whether the emmc2bus alias is defined, and if
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* so, it'll edit the dma-ranges property below accordingly.
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*/
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emmc2bus: emmc2bus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
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dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
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emmc2: emmc2@7e340000 {
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compatible = "brcm,bcm2711-emmc2";
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reg = <0x0 0x7e340000 0x100>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clocks BCM2711_CLOCK_EMMC2>;
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status = "disabled";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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/* This only applies to the ARMv7 stub */
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arm,cpu-registers-not-fw-configured;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000d8>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e8>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000f0>;
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};
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};
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scb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
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<0x6 0x00000000 0x6 0x00000000 0x40000000>;
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pcie0: pcie@7d500000 {
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compatible = "brcm,bcm2711-pcie";
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reg = <0x0 0x7d500000 0x9310>;
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device_type = "pci";
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
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IRQ_TYPE_LEVEL_HIGH>;
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msi-controller;
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msi-parent = <&pcie0>;
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ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
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0x0 0x04000000>;
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/*
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* The wrapper around the PCIe block has a bug
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* preventing it from accessing beyond the first 3GB of
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* memory.
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*/
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dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
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0x0 0xc0000000>;
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brcm,enable-ssc;
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};
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genet: ethernet@7d580000 {
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compatible = "brcm,bcm2711-genet-v5";
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reg = <0x0 0x7d580000 0x10000>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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genet_mdio: mdio@e14 {
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compatible = "brcm,genet-mdio-v5";
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reg = <0xe14 0x8>;
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reg-names = "mdio";
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#address-cells = <0x0>;
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#size-cells = <0x1>;
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};
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};
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};
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};
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&clk_osc {
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clock-frequency = <54000000>;
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};
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&clocks {
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compatible = "brcm,bcm2711-cprman";
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};
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&cpu_thermal {
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coefficients = <(-487) 410040>;
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thermal-sensors = <&thermal>;
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};
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&dsi0 {
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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};
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&dsi1 {
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio {
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compatible = "brcm,bcm2711-gpio";
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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gpclk0_gpio49: gpclk0_gpio49 {
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pin-gpclk {
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pins = "gpio49";
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function = "alt1";
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bias-disable;
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};
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};
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gpclk1_gpio50: gpclk1_gpio50 {
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pin-gpclk {
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pins = "gpio50";
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function = "alt1";
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bias-disable;
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};
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};
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gpclk2_gpio51: gpclk2_gpio51 {
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pin-gpclk {
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pins = "gpio51";
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function = "alt1";
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bias-disable;
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};
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};
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i2c0_gpio46: i2c0_gpio46 {
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pin-sda {
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function = "alt0";
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pins = "gpio46";
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bias-pull-up;
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};
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pin-scl {
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function = "alt0";
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pins = "gpio47";
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bias-disable;
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};
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};
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i2c1_gpio46: i2c1_gpio46 {
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pin-sda {
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function = "alt1";
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pins = "gpio46";
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bias-pull-up;
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};
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pin-scl {
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function = "alt1";
|
|
pins = "gpio47";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c3_gpio2: i2c3_gpio2 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio2";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio3";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c3_gpio4: i2c3_gpio4 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio4";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio5";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c4_gpio6: i2c4_gpio6 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio6";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio7";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c4_gpio8: i2c4_gpio8 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio8";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio9";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c5_gpio10: i2c5_gpio10 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio10";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio11";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c5_gpio12: i2c5_gpio12 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio12";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio13";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c6_gpio0: i2c6_gpio0 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio0";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio1";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c6_gpio22: i2c6_gpio22 {
|
|
pin-sda {
|
|
function = "alt5";
|
|
pins = "gpio22";
|
|
bias-pull-up;
|
|
};
|
|
pin-scl {
|
|
function = "alt5";
|
|
pins = "gpio23";
|
|
bias-disable;
|
|
};
|
|
};
|
|
i2c_slave_gpio8: i2c_slave_gpio8 {
|
|
pins-i2c-slave {
|
|
pins = "gpio8",
|
|
"gpio9",
|
|
"gpio10",
|
|
"gpio11";
|
|
function = "alt3";
|
|
};
|
|
};
|
|
|
|
jtag_gpio48: jtag_gpio48 {
|
|
pins-jtag {
|
|
pins = "gpio48",
|
|
"gpio49",
|
|
"gpio50",
|
|
"gpio51",
|
|
"gpio52",
|
|
"gpio53";
|
|
function = "alt4";
|
|
};
|
|
};
|
|
|
|
mii_gpio28: mii_gpio28 {
|
|
pins-mii {
|
|
pins = "gpio28",
|
|
"gpio29",
|
|
"gpio30",
|
|
"gpio31";
|
|
function = "alt4";
|
|
};
|
|
};
|
|
mii_gpio36: mii_gpio36 {
|
|
pins-mii {
|
|
pins = "gpio36",
|
|
"gpio37",
|
|
"gpio38",
|
|
"gpio39";
|
|
function = "alt5";
|
|
};
|
|
};
|
|
|
|
pcm_gpio50: pcm_gpio50 {
|
|
pins-pcm {
|
|
pins = "gpio50",
|
|
"gpio51",
|
|
"gpio52",
|
|
"gpio53";
|
|
function = "alt2";
|
|
};
|
|
};
|
|
|
|
pwm0_0_gpio12: pwm0_0_gpio12 {
|
|
pin-pwm {
|
|
pins = "gpio12";
|
|
function = "alt0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_0_gpio18: pwm0_0_gpio18 {
|
|
pin-pwm {
|
|
pins = "gpio18";
|
|
function = "alt5";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm1_0_gpio40: pwm1_0_gpio40 {
|
|
pin-pwm {
|
|
pins = "gpio40";
|
|
function = "alt0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_1_gpio13: pwm0_1_gpio13 {
|
|
pin-pwm {
|
|
pins = "gpio13";
|
|
function = "alt0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_1_gpio19: pwm0_1_gpio19 {
|
|
pin-pwm {
|
|
pins = "gpio19";
|
|
function = "alt5";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm1_1_gpio41: pwm1_1_gpio41 {
|
|
pin-pwm {
|
|
pins = "gpio41";
|
|
function = "alt0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_1_gpio45: pwm0_1_gpio45 {
|
|
pin-pwm {
|
|
pins = "gpio45";
|
|
function = "alt0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_0_gpio52: pwm0_0_gpio52 {
|
|
pin-pwm {
|
|
pins = "gpio52";
|
|
function = "alt1";
|
|
bias-disable;
|
|
};
|
|
};
|
|
pwm0_1_gpio53: pwm0_1_gpio53 {
|
|
pin-pwm {
|
|
pins = "gpio53";
|
|
function = "alt1";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
rgmii_gpio35: rgmii_gpio35 {
|
|
pin-start-stop {
|
|
pins = "gpio35";
|
|
function = "alt4";
|
|
};
|
|
pin-rx-ok {
|
|
pins = "gpio36";
|
|
function = "alt4";
|
|
};
|
|
};
|
|
rgmii_irq_gpio34: rgmii_irq_gpio34 {
|
|
pin-irq {
|
|
pins = "gpio34";
|
|
function = "alt5";
|
|
};
|
|
};
|
|
rgmii_irq_gpio39: rgmii_irq_gpio39 {
|
|
pin-irq {
|
|
pins = "gpio39";
|
|
function = "alt4";
|
|
};
|
|
};
|
|
rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
|
|
pins-mdio {
|
|
pins = "gpio28",
|
|
"gpio29";
|
|
function = "alt5";
|
|
};
|
|
};
|
|
rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
|
|
pins-mdio {
|
|
pins = "gpio37",
|
|
"gpio38";
|
|
function = "alt4";
|
|
};
|
|
};
|
|
|
|
spi0_gpio46: spi0_gpio46 {
|
|
pins-spi {
|
|
pins = "gpio46",
|
|
"gpio47",
|
|
"gpio48",
|
|
"gpio49";
|
|
function = "alt2";
|
|
};
|
|
};
|
|
spi2_gpio46: spi2_gpio46 {
|
|
pins-spi {
|
|
pins = "gpio46",
|
|
"gpio47",
|
|
"gpio48",
|
|
"gpio49",
|
|
"gpio50";
|
|
function = "alt5";
|
|
};
|
|
};
|
|
spi3_gpio0: spi3_gpio0 {
|
|
pins-spi {
|
|
pins = "gpio0",
|
|
"gpio1",
|
|
"gpio2",
|
|
"gpio3";
|
|
function = "alt3";
|
|
};
|
|
};
|
|
spi4_gpio4: spi4_gpio4 {
|
|
pins-spi {
|
|
pins = "gpio4",
|
|
"gpio5",
|
|
"gpio6",
|
|
"gpio7";
|
|
function = "alt3";
|
|
};
|
|
};
|
|
spi5_gpio12: spi5_gpio12 {
|
|
pins-spi {
|
|
pins = "gpio12",
|
|
"gpio13",
|
|
"gpio14",
|
|
"gpio15";
|
|
function = "alt3";
|
|
};
|
|
};
|
|
spi6_gpio18: spi6_gpio18 {
|
|
pins-spi {
|
|
pins = "gpio18",
|
|
"gpio19",
|
|
"gpio20",
|
|
"gpio21";
|
|
function = "alt3";
|
|
};
|
|
};
|
|
|
|
uart2_gpio0: uart2_gpio0 {
|
|
pin-tx {
|
|
pins = "gpio0";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
pin-rx {
|
|
pins = "gpio1";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
|
|
pin-cts {
|
|
pins = "gpio2";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
pin-rts {
|
|
pins = "gpio3";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
};
|
|
uart3_gpio4: uart3_gpio4 {
|
|
pin-tx {
|
|
pins = "gpio4";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
pin-rx {
|
|
pins = "gpio5";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
|
|
pin-cts {
|
|
pins = "gpio6";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
pin-rts {
|
|
pins = "gpio7";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
};
|
|
uart4_gpio8: uart4_gpio8 {
|
|
pin-tx {
|
|
pins = "gpio8";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
pin-rx {
|
|
pins = "gpio9";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
|
|
pin-cts {
|
|
pins = "gpio10";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
pin-rts {
|
|
pins = "gpio11";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
};
|
|
uart5_gpio12: uart5_gpio12 {
|
|
pin-tx {
|
|
pins = "gpio12";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
pin-rx {
|
|
pins = "gpio13";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
|
|
pin-cts {
|
|
pins = "gpio14";
|
|
function = "alt4";
|
|
bias-pull-up;
|
|
};
|
|
pin-rts {
|
|
pins = "gpio15";
|
|
function = "alt4";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rmem {
|
|
#address-cells = <2>;
|
|
};
|
|
|
|
&cma {
|
|
/*
|
|
* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
|
|
* that's not good enough for the BCM2711 as some devices can
|
|
* only address the lower 1G of memory (ZONE_DMA).
|
|
*/
|
|
alloc-ranges = <0x0 0x00000000 0x40000000>;
|
|
};
|
|
|
|
&i2c0 {
|
|
compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&i2c1 {
|
|
compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&mailbox {
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&sdhci {
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&sdhost {
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&spi {
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&spi1 {
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&spi2 {
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&system_timer {
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&txp {
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&uart0 {
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&uart1 {
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&usb {
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
&vec {
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|