mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 15:36:44 +07:00
5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
470 lines
11 KiB
C
470 lines
11 KiB
C
/*
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* 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
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* such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
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* like hx4700).
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*
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* Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
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* Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
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*
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* Use consistent with the GNU GPL is permitted,
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* provided that this copyright notice is
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* preserved in its entirety in all copies and derived works.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ds1wm.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include "../w1.h"
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#include "../w1_int.h"
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#define DS1WM_CMD 0x00 /* R/W 4 bits command */
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#define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */
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#define DS1WM_INT 0x02 /* R/W interrupt status */
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#define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
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#define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
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#define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
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#define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
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#define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */
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#define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */
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#define DS1WM_CMD_RST (1 << 5) /* software reset */
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#define DS1WM_CMD_OD (1 << 7) /* overdrive */
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#define DS1WM_INT_PD (1 << 0) /* presence detect */
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#define DS1WM_INT_PDR (1 << 1) /* presence detect result */
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#define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */
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#define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */
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#define DS1WM_INT_RBF (1 << 4) /* rx buffer full */
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#define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */
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#define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */
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#define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */
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#define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */
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#define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */
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#define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */
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#define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
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#define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
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#define DS1WM_TIMEOUT (HZ * 5)
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static struct {
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unsigned long freq;
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unsigned long divisor;
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} freq[] = {
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{ 4000000, 0x8 },
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{ 5000000, 0x2 },
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{ 6000000, 0x5 },
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{ 7000000, 0x3 },
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{ 8000000, 0xc },
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{ 10000000, 0x6 },
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{ 12000000, 0x9 },
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{ 14000000, 0x7 },
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{ 16000000, 0x10 },
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{ 20000000, 0xa },
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{ 24000000, 0xd },
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{ 28000000, 0xb },
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{ 32000000, 0x14 },
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{ 40000000, 0xe },
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{ 48000000, 0x11 },
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{ 56000000, 0xf },
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{ 64000000, 0x18 },
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{ 80000000, 0x12 },
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{ 96000000, 0x15 },
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{ 112000000, 0x13 },
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{ 128000000, 0x1c },
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};
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struct ds1wm_data {
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void __iomem *map;
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int bus_shift; /* # of shifts to calc register offsets */
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struct platform_device *pdev;
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struct mfd_cell *cell;
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int irq;
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int active_high;
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int slave_present;
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void *reset_complete;
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void *read_complete;
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void *write_complete;
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u8 read_byte; /* last byte received */
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};
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static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
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u8 val)
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{
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__raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
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}
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static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
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{
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return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
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}
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static irqreturn_t ds1wm_isr(int isr, void *data)
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{
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struct ds1wm_data *ds1wm_data = data;
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u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
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ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
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if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
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complete(ds1wm_data->reset_complete);
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if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
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complete(ds1wm_data->write_complete);
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if (intr & DS1WM_INT_RBF) {
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ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
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DS1WM_DATA);
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if (ds1wm_data->read_complete)
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complete(ds1wm_data->read_complete);
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}
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return IRQ_HANDLED;
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}
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static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
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{
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unsigned long timeleft;
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DECLARE_COMPLETION_ONSTACK(reset_done);
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ds1wm_data->reset_complete = &reset_done;
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
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(ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
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timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
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ds1wm_data->reset_complete = NULL;
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if (!timeleft) {
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dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
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return 1;
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}
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/* Wait for the end of the reset. According to the specs, the time
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* from when the interrupt is asserted to the end of the reset is:
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* tRSTH - tPDH - tPDL - tPDI
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* 625 us - 60 us - 240 us - 100 ns = 324.9 us
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*
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* We'll wait a bit longer just to be sure.
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* Was udelay(500), but if it is going to busywait the cpu that long,
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* might as well come back later.
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*/
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msleep(1);
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
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DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
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(ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
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if (!ds1wm_data->slave_present) {
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dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
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return 1;
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}
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return 0;
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}
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static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
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{
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DECLARE_COMPLETION_ONSTACK(write_done);
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ds1wm_data->write_complete = &write_done;
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ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
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wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
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ds1wm_data->write_complete = NULL;
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return 0;
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}
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static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
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{
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DECLARE_COMPLETION_ONSTACK(read_done);
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ds1wm_data->read_complete = &read_done;
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ds1wm_write(ds1wm_data, write_data);
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wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
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ds1wm_data->read_complete = NULL;
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return ds1wm_data->read_byte;
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}
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static int ds1wm_find_divisor(int gclk)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(freq); i++)
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if (gclk <= freq[i].freq)
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return freq[i].divisor;
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return 0;
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}
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static void ds1wm_up(struct ds1wm_data *ds1wm_data)
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{
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int divisor;
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struct ds1wm_driver_data *plat = ds1wm_data->cell->driver_data;
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if (ds1wm_data->cell->enable)
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ds1wm_data->cell->enable(ds1wm_data->pdev);
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divisor = ds1wm_find_divisor(plat->clock_rate);
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if (divisor == 0) {
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dev_err(&ds1wm_data->pdev->dev,
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"no suitable divisor for %dHz clock\n",
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plat->clock_rate);
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return;
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}
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ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
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/* Let the w1 clock stabilize. */
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msleep(1);
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ds1wm_reset(ds1wm_data);
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}
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static void ds1wm_down(struct ds1wm_data *ds1wm_data)
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{
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ds1wm_reset(ds1wm_data);
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/* Disable interrupts. */
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ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
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ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
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if (ds1wm_data->cell->disable)
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ds1wm_data->cell->disable(ds1wm_data->pdev);
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}
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/* --------------------------------------------------------------------- */
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/* w1 methods */
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static u8 ds1wm_read_byte(void *data)
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{
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struct ds1wm_data *ds1wm_data = data;
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return ds1wm_read(ds1wm_data, 0xff);
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}
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static void ds1wm_write_byte(void *data, u8 byte)
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{
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struct ds1wm_data *ds1wm_data = data;
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ds1wm_write(ds1wm_data, byte);
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}
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static u8 ds1wm_reset_bus(void *data)
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{
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struct ds1wm_data *ds1wm_data = data;
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ds1wm_reset(ds1wm_data);
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return 0;
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}
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static void ds1wm_search(void *data, struct w1_master *master_dev,
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u8 search_type, w1_slave_found_callback slave_found)
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{
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struct ds1wm_data *ds1wm_data = data;
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int i;
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unsigned long long rom_id;
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/* XXX We need to iterate for multiple devices per the DS1WM docs.
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* See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
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if (ds1wm_reset(ds1wm_data))
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return;
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ds1wm_write(ds1wm_data, search_type);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
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for (rom_id = 0, i = 0; i < 16; i++) {
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unsigned char resp, r, d;
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resp = ds1wm_read(ds1wm_data, 0x00);
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r = ((resp & 0x02) >> 1) |
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((resp & 0x08) >> 2) |
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((resp & 0x20) >> 3) |
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((resp & 0x80) >> 4);
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d = ((resp & 0x01) >> 0) |
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((resp & 0x04) >> 1) |
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((resp & 0x10) >> 2) |
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((resp & 0x40) >> 3);
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rom_id |= (unsigned long long) r << (i * 4);
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}
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dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
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ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
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ds1wm_reset(ds1wm_data);
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slave_found(master_dev, rom_id);
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}
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/* --------------------------------------------------------------------- */
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static struct w1_bus_master ds1wm_master = {
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.read_byte = ds1wm_read_byte,
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.write_byte = ds1wm_write_byte,
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.reset_bus = ds1wm_reset_bus,
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.search = ds1wm_search,
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};
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static int ds1wm_probe(struct platform_device *pdev)
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{
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struct ds1wm_data *ds1wm_data;
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struct ds1wm_driver_data *plat;
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struct resource *res;
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struct mfd_cell *cell;
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int ret;
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if (!pdev)
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return -ENODEV;
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cell = pdev->dev.platform_data;
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if (!cell)
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return -ENODEV;
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ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
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if (!ds1wm_data)
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return -ENOMEM;
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platform_set_drvdata(pdev, ds1wm_data);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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ret = -ENXIO;
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goto err0;
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}
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ds1wm_data->map = ioremap(res->start, resource_size(res));
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if (!ds1wm_data->map) {
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ret = -ENOMEM;
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goto err0;
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}
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plat = cell->driver_data;
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/* calculate bus shift from mem resource */
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ds1wm_data->bus_shift = resource_size(res) >> 3;
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ds1wm_data->pdev = pdev;
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ds1wm_data->cell = cell;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res) {
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ret = -ENXIO;
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goto err1;
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}
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ds1wm_data->irq = res->start;
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ds1wm_data->active_high = plat->active_high;
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if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
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set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
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if (res->flags & IORESOURCE_IRQ_LOWEDGE)
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set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
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ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
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"ds1wm", ds1wm_data);
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if (ret)
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goto err1;
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ds1wm_up(ds1wm_data);
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ds1wm_master.data = (void *)ds1wm_data;
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ret = w1_add_master_device(&ds1wm_master);
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if (ret)
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goto err2;
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return 0;
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err2:
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ds1wm_down(ds1wm_data);
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free_irq(ds1wm_data->irq, ds1wm_data);
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err1:
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iounmap(ds1wm_data->map);
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err0:
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kfree(ds1wm_data);
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return ret;
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}
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#ifdef CONFIG_PM
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static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
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ds1wm_down(ds1wm_data);
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return 0;
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}
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static int ds1wm_resume(struct platform_device *pdev)
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{
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struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
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ds1wm_up(ds1wm_data);
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return 0;
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}
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#else
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#define ds1wm_suspend NULL
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#define ds1wm_resume NULL
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#endif
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static int ds1wm_remove(struct platform_device *pdev)
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{
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struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
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w1_remove_master_device(&ds1wm_master);
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ds1wm_down(ds1wm_data);
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free_irq(ds1wm_data->irq, ds1wm_data);
|
|
iounmap(ds1wm_data->map);
|
|
kfree(ds1wm_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ds1wm_driver = {
|
|
.driver = {
|
|
.name = "ds1wm",
|
|
},
|
|
.probe = ds1wm_probe,
|
|
.remove = ds1wm_remove,
|
|
.suspend = ds1wm_suspend,
|
|
.resume = ds1wm_resume
|
|
};
|
|
|
|
static int __init ds1wm_init(void)
|
|
{
|
|
printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
|
|
return platform_driver_register(&ds1wm_driver);
|
|
}
|
|
|
|
static void __exit ds1wm_exit(void)
|
|
{
|
|
platform_driver_unregister(&ds1wm_driver);
|
|
}
|
|
|
|
module_init(ds1wm_init);
|
|
module_exit(ds1wm_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
|
|
"Matt Reimer <mreimer@vpop.net>");
|
|
MODULE_DESCRIPTION("DS1WM w1 busmaster driver");
|