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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e36361d70e
This implements an earlycon for Actions Semi S500/S900 SoCs. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
/*
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* Actions Semi Owl family serial console
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*
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* Copyright 2013 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2016-2017 Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#define OWL_UART_CTL 0x000
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#define OWL_UART_TXDAT 0x008
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#define OWL_UART_STAT 0x00c
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#define OWL_UART_CTL_TRFS_TX BIT(14)
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#define OWL_UART_CTL_EN BIT(15)
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#define OWL_UART_CTL_RXIE BIT(18)
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#define OWL_UART_CTL_TXIE BIT(19)
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#define OWL_UART_STAT_RIP BIT(0)
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#define OWL_UART_STAT_TIP BIT(1)
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#define OWL_UART_STAT_TFFU BIT(6)
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#define OWL_UART_STAT_TRFL_MASK (0x1f << 11)
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#define OWL_UART_STAT_UTBB BIT(17)
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static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
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{
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writel(val, port->membase + off);
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}
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static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
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{
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return readl(port->membase + off);
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}
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#ifdef CONFIG_SERIAL_OWL_CONSOLE
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static void owl_console_putchar(struct uart_port *port, int ch)
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{
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if (!port->membase)
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return;
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while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
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cpu_relax();
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owl_uart_write(port, ch, OWL_UART_TXDAT);
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}
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static void owl_uart_port_write(struct uart_port *port, const char *s,
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u_int count)
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{
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u32 old_ctl, val;
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unsigned long flags;
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int locked;
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local_irq_save(flags);
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if (port->sysrq)
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locked = 0;
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else if (oops_in_progress)
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locked = spin_trylock(&port->lock);
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else {
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spin_lock(&port->lock);
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locked = 1;
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}
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old_ctl = owl_uart_read(port, OWL_UART_CTL);
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val = old_ctl | OWL_UART_CTL_TRFS_TX;
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/* disable IRQ */
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val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
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owl_uart_write(port, val, OWL_UART_CTL);
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uart_console_write(port, s, count, owl_console_putchar);
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/* wait until all contents have been sent out */
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while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
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cpu_relax();
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/* clear IRQ pending */
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val = owl_uart_read(port, OWL_UART_STAT);
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val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
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owl_uart_write(port, val, OWL_UART_STAT);
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owl_uart_write(port, old_ctl, OWL_UART_CTL);
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if (locked)
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spin_unlock(&port->lock);
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local_irq_restore(flags);
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}
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static void owl_uart_early_console_write(struct console *co,
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const char *s,
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u_int count)
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{
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struct earlycon_device *dev = co->data;
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owl_uart_port_write(&dev->port, s, count);
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}
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static int __init
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owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
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{
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if (!device->port.membase)
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return -ENODEV;
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device->con->write = owl_uart_early_console_write;
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return 0;
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}
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OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
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owl_uart_early_console_setup);
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#endif /* CONFIG_SERIAL_OWL_CONSOLE */
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