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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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02c981c07b
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
/*
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* interrupt controller support for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <asm/mach/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define SIRFSOC_INT_RISC_MASK0 0x0018
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#define SIRFSOC_INT_RISC_MASK1 0x001C
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#define SIRFSOC_INT_RISC_LEVEL0 0x0020
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#define SIRFSOC_INT_RISC_LEVEL1 0x0024
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void __iomem *sirfsoc_intc_base;
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static __init void
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sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
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}
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static __init void sirfsoc_irq_init(void)
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{
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sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
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sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
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writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
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}
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static struct of_device_id intc_ids[] = {
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{ .compatible = "sirf,prima2-intc" },
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};
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void __init sirfsoc_of_irq_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, intc_ids);
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if (!np)
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panic("unable to find compatible intc node in dtb\n");
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sirfsoc_intc_base = of_iomap(np, 0);
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if (!sirfsoc_intc_base)
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panic("unable to map intc cpu registers\n");
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of_node_put(np);
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sirfsoc_irq_init();
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}
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