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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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39e9af3de5
Each thread has an associated Thread Interrupt Management context
composed of a set of registers. These registers let the thread handle
priority management and interrupt acknowledgment. The most important
are :
- Interrupt Pending Buffer (IPB)
- Current Processor Priority (CPPR)
- Notification Source Register (NSR)
They are exposed to software in four different pages each proposing a
view with a different privilege. The first page is for the physical
thread context and the second for the hypervisor. Only the third
(operating system) and the fourth (user level) are exposed the guest.
A custom VM fault handler will populate the VMA with the appropriate
pages, which should only be the OS page for now.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
155 lines
4.8 KiB
C
155 lines
4.8 KiB
C
/*
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* Copyright 2016,2017 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_XIVE_H
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#define _ASM_POWERPC_XIVE_H
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#define XIVE_INVALID_VP 0xffffffff
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#ifdef CONFIG_PPC_XIVE
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/*
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* Thread Interrupt Management Area (TIMA)
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*
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* This is a global MMIO region divided in 4 pages of varying access
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* permissions, providing access to per-cpu interrupt management
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* functions. It always identifies the CPU doing the access based
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* on the PowerBus initiator ID, thus we always access via the
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* same offset regardless of where the code is executing
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*/
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extern void __iomem *xive_tima;
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extern unsigned long xive_tima_os;
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/*
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* Offset in the TM area of our current execution level (provided by
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* the backend)
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*/
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extern u32 xive_tima_offset;
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/*
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* Per-irq data (irq_get_handler_data for normal IRQs), IPIs
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* have it stored in the xive_cpu structure. We also cache
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* for normal interrupts the current target CPU.
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*
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* This structure is setup by the backend for each interrupt.
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*/
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struct xive_irq_data {
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u64 flags;
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u64 eoi_page;
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void __iomem *eoi_mmio;
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u64 trig_page;
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void __iomem *trig_mmio;
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u32 esb_shift;
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int src_chip;
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u32 hw_irq;
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/* Setup/used by frontend */
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int target;
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bool saved_p;
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};
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#define XIVE_IRQ_FLAG_STORE_EOI 0x01
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#define XIVE_IRQ_FLAG_LSI 0x02
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#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
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#define XIVE_IRQ_FLAG_MASK_FW 0x08
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#define XIVE_IRQ_FLAG_EOI_FW 0x10
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#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
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/* Special flag set by KVM for excalation interrupts */
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#define XIVE_IRQ_NO_EOI 0x80
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#define XIVE_INVALID_CHIP_ID -1
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/* A queue tracking structure in a CPU */
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struct xive_q {
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__be32 *qpage;
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u32 msk;
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u32 idx;
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u32 toggle;
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u64 eoi_phys;
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u32 esc_irq;
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atomic_t count;
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atomic_t pending_count;
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u64 guest_qaddr;
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u32 guest_qshift;
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};
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/* Global enable flags for the XIVE support */
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extern bool __xive_enabled;
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static inline bool xive_enabled(void) { return __xive_enabled; }
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extern bool xive_spapr_init(void);
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extern bool xive_native_init(void);
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extern void xive_smp_probe(void);
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extern int xive_smp_prepare_cpu(unsigned int cpu);
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extern void xive_smp_setup_cpu(void);
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extern void xive_smp_disable_cpu(void);
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extern void xive_teardown_cpu(void);
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extern void xive_shutdown(void);
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extern void xive_flush_interrupt(void);
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/* xmon hook */
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extern void xmon_xive_do_dump(int cpu);
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/* APIs used by KVM */
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extern u32 xive_native_default_eq_shift(void);
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extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
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extern void xive_native_free_vp_block(u32 vp_base);
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extern int xive_native_populate_irq_data(u32 hw_irq,
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struct xive_irq_data *data);
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extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
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extern u32 xive_native_alloc_irq(void);
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extern void xive_native_free_irq(u32 irq);
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extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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__be32 *qpage, u32 order, bool can_escalate);
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extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
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extern void xive_native_sync_source(u32 hw_irq);
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extern void xive_native_sync_queue(u32 hw_irq);
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extern bool is_xive_irq(struct irq_chip *chip);
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extern int xive_native_enable_vp(u32 vp_id, bool single_escalation);
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extern int xive_native_disable_vp(u32 vp_id);
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extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
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extern bool xive_native_has_single_escalation(void);
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extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
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u64 *out_qpage,
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u64 *out_qsize,
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u64 *out_qeoi_page,
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u32 *out_escalate_irq,
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u64 *out_qflags);
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extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
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u32 *qindex);
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extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
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u32 qindex);
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extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
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#else
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static inline bool xive_enabled(void) { return false; }
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static inline bool xive_spapr_init(void) { return false; }
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static inline bool xive_native_init(void) { return false; }
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static inline void xive_smp_probe(void) { }
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static inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
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static inline void xive_smp_setup_cpu(void) { }
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static inline void xive_smp_disable_cpu(void) { }
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static inline void xive_kexec_teardown_cpu(int secondary) { }
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static inline void xive_shutdown(void) { }
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static inline void xive_flush_interrupt(void) { }
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static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
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static inline void xive_native_free_vp_block(u32 vp_base) { }
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#endif
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#endif /* _ASM_POWERPC_XIVE_H */
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