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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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de269129a4
On TOD/TB errors timebase register stops/freezes until HMI error recovery gets TOD/TB back into running state. On successful recovery, TB starts running again and udelay() that relies on TB value continues to function properly. But in case when HMI fails to recover from TOD/TB errors, the TB register stay freezed. With TB not running the __delay() function keeps looping and never return. If __delay() is called while in panic path then system hangs and never reboots after panic. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
400 lines
17 KiB
C
400 lines
17 KiB
C
/*
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* PowerNV OPAL definitions.
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_OPAL_H
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#define _ASM_POWERPC_OPAL_H
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#include <asm/opal-api.h>
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#ifndef __ASSEMBLY__
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#include <linux/notifier.h>
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/* We calculate number of sg entries based on PAGE_SIZE */
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#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
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/* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
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#define OPAL_BUSY_DELAY_MS 10
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/* /sys/firmware/opal */
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extern struct kobject *opal_kobj;
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/* /ibm,opal */
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extern struct device_node *opal_node;
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/* API functions */
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int64_t opal_invalid_call(void);
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int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
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int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
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uint64_t bdf);
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int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
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uint64_t lpcr);
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int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
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uint64_t addr, uint64_t PE_mask);
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int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
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uint64_t PE_handle);
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int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
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uint64_t rate_phys, uint32_t size);
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int64_t opal_console_write(int64_t term_number, __be64 *length,
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const uint8_t *buffer);
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int64_t opal_console_read(int64_t term_number, __be64 *length,
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uint8_t *buffer);
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int64_t opal_console_write_buffer_space(int64_t term_number,
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__be64 *length);
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int64_t opal_console_flush(int64_t term_number);
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int64_t opal_rtc_read(__be32 *year_month_day,
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__be64 *hour_minute_second_millisecond);
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int64_t opal_rtc_write(uint32_t year_month_day,
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uint64_t hour_minute_second_millisecond);
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int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
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int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
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uint32_t hour_min);
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int64_t opal_cec_power_down(uint64_t request);
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int64_t opal_cec_reboot(void);
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int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
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int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
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int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
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int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
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int64_t opal_poll_events(__be64 *outstanding_event_mask);
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int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
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uint64_t tce_mem_size);
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int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
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uint64_t tce_mem_size);
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int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint8_t *data);
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int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, __be16 *data);
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int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, __be32 *data);
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int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint8_t data);
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int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint16_t data);
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int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint32_t data);
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int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
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int64_t opal_register_exception_handler(uint64_t opal_exception,
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uint64_t handler_address,
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uint64_t glue_cache_line);
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int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
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uint8_t *freeze_state,
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__be16 *pci_error_type,
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__be64 *phb_status);
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int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
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uint64_t eeh_action_token);
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int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
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uint64_t eeh_action_token);
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int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
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uint32_t func, uint64_t addr, uint64_t mask);
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int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
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int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
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uint16_t window_num, uint16_t enable);
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int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
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uint16_t window_num,
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uint64_t starting_real_address,
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uint64_t starting_pci_address,
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uint64_t size);
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int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
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uint16_t window_type, uint16_t window_num,
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uint16_t segment_num);
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int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
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uint64_t ivt_addr, uint64_t ivt_len,
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uint64_t reject_array_addr,
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uint64_t peltv_addr);
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int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
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uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
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uint8_t pe_action);
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int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
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uint8_t state);
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int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
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int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
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uint32_t state);
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int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
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uint8_t *p_bit, uint8_t *q_bit);
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int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
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uint8_t p_bit, uint8_t q_bit);
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int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
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int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
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uint32_t xive_num);
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int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
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__be32 *interrupt_source_number);
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int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
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uint8_t msi_range, __be32 *msi_address,
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__be32 *message_data);
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int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
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uint32_t xive_num, uint8_t msi_range,
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__be64 *msi_address, __be32 *message_data);
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int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
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int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
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int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
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int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
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uint16_t tce_levels, uint64_t tce_table_addr,
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uint64_t tce_table_size, uint64_t tce_page_size);
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int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
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uint16_t dma_window_number, uint64_t pci_start_addr,
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uint64_t pci_mem_size);
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int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
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int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_fence_phb(uint64_t phb_id);
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int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
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int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
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int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
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int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
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int64_t opal_get_dpo_status(__be64 *dpo_timeout);
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int64_t opal_set_system_attention_led(uint8_t led_action);
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int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
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__be16 *pci_error_type, __be16 *severity);
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int64_t opal_pci_poll(uint64_t id);
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int64_t opal_return_cpu(void);
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int64_t opal_check_token(uint64_t token);
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int64_t opal_reinit_cpus(uint64_t flags);
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int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
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int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
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int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
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uint32_t addr, uint32_t data, uint32_t sz);
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int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
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uint32_t addr, __be32 *data, uint32_t sz);
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int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
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int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
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int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
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int64_t opal_send_ack_elog(uint64_t log_id);
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void opal_resend_pending_logs(void);
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int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
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int64_t opal_manage_flash(uint8_t op);
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int64_t opal_update_flash(uint64_t blk_list);
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int64_t opal_dump_init(uint8_t dump_type);
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int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
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int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
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int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
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int64_t opal_dump_ack(uint32_t dump_id);
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int64_t opal_dump_resend_notification(void);
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int64_t opal_get_msg(uint64_t buffer, uint64_t size);
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int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
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uint64_t num_lines);
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int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
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int64_t opal_sync_host_reboot(void);
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int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
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uint64_t length);
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int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
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uint64_t length);
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int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
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int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
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int64_t opal_handle_hmi(void);
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int64_t opal_handle_hmi2(__be64 *out_flags);
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int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
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int64_t opal_unregister_dump_region(uint32_t id);
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int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
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int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
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int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
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int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
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int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
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int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
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uint64_t msg_len);
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int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
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uint64_t *msg_len);
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int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
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struct opal_i2c_request *oreq);
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int64_t opal_prd_msg(struct opal_prd_msg *msg);
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int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
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__be64 *led_value, __be64 *max_led_type);
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int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
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const u64 led_value, __be64 *max_led_type);
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int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
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uint64_t size, uint64_t token);
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int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
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uint64_t size, uint64_t token);
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int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
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uint64_t token);
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int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
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int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
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int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
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int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
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uint64_t data);
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int64_t opal_pci_poll2(uint64_t id, uint64_t data);
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int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
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int64_t opal_int_set_cppr(uint8_t cppr);
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int64_t opal_int_eoi(uint32_t xirr);
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int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
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int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
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uint32_t pe_num, uint32_t tce_size,
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uint64_t dma_addr, uint32_t npages);
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int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
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int64_t opal_xive_reset(uint64_t version);
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int64_t opal_xive_get_irq_info(uint32_t girq,
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__be64 *out_flags,
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__be64 *out_eoi_page,
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__be64 *out_trig_page,
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__be32 *out_esb_shift,
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__be32 *out_src_chip);
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int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
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uint8_t *out_prio, __be32 *out_lirq);
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int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
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uint32_t lirq);
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int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
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__be64 *out_qpage,
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__be64 *out_qsize,
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__be64 *out_qeoi_page,
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__be32 *out_escalate_irq,
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__be64 *out_qflags);
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int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
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uint64_t qpage,
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uint64_t qsize,
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uint64_t qflags);
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int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
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int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
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int64_t opal_xive_free_vp_block(uint64_t vp);
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int64_t opal_xive_get_vp_info(uint64_t vp,
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__be64 *out_flags,
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__be64 *out_cam_value,
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__be64 *out_report_cl_pair,
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__be32 *out_chip_id);
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int64_t opal_xive_set_vp_info(uint64_t vp,
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uint64_t flags,
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uint64_t report_cl_pair);
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int64_t opal_xive_allocate_irq(uint32_t chip_id);
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int64_t opal_xive_free_irq(uint32_t girq);
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int64_t opal_xive_sync(uint32_t type, uint32_t id);
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int64_t opal_xive_dump(uint32_t type, uint32_t id);
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int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
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__be32 *out_qtoggle,
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__be32 *out_qindex);
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int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
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uint32_t qtoggle,
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uint32_t qindex);
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int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
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int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
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uint64_t desc, uint16_t pe_number);
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int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
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uint64_t cpu_pir);
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int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
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int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
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int opal_get_powercap(u32 handle, int token, u32 *pcap);
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int opal_set_powercap(u32 handle, int token, u32 pcap);
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int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
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int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
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int opal_sensor_group_clear(u32 group_hndl, int token);
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int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
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int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
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s64 opal_signal_system_reset(s32 cpu);
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s64 opal_quiesce(u64 shutdown_type, s32 cpu);
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
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int depth, void *data);
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extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
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const char *uname, int depth, void *data);
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extern void opal_configure_cores(void);
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extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
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extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
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extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
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extern int opal_flush_chars(uint32_t vtermno, bool wait);
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extern int opal_flush_console(uint32_t vtermno);
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extern void hvc_opal_init_early(void);
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extern int opal_notifier_register(struct notifier_block *nb);
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extern int opal_notifier_unregister(struct notifier_block *nb);
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extern int opal_message_notifier_register(enum opal_msg_type msg_type,
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struct notifier_block *nb);
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extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
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struct notifier_block *nb);
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extern void opal_notifier_enable(void);
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extern void opal_notifier_disable(void);
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extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
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extern int opal_async_get_token_interruptible(void);
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extern int opal_async_release_token(int token);
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extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
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extern int opal_async_wait_response_interruptible(uint64_t token,
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struct opal_msg *msg);
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extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
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extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
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extern int sensor_group_enable(u32 grp_hndl, bool enable);
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struct rtc_time;
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extern time64_t opal_get_boot_time(void);
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extern void opal_nvram_init(void);
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extern void opal_flash_update_init(void);
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extern void opal_flash_update_print_message(void);
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extern int opal_elog_init(void);
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extern void opal_platform_dump_init(void);
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extern void opal_sys_param_init(void);
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extern void opal_msglog_init(void);
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extern void opal_msglog_sysfs_init(void);
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extern int opal_async_comp_init(void);
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extern int opal_sensor_init(void);
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extern int opal_hmi_handler_init(void);
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extern int opal_event_init(void);
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int opal_power_control_init(void);
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extern int opal_machine_check(struct pt_regs *regs);
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extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
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extern int opal_hmi_exception_early(struct pt_regs *regs);
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extern int opal_hmi_exception_early2(struct pt_regs *regs);
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extern int opal_handle_hmi_exception(struct pt_regs *regs);
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extern void opal_shutdown(void);
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extern int opal_resync_timebase(void);
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|
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extern void opal_lpc_init(void);
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|
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extern void opal_kmsg_init(void);
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|
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extern int opal_event_request(unsigned int opal_event_nr);
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|
|
|
struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
|
|
unsigned long vmalloc_size);
|
|
void opal_free_sg_list(struct opal_sg_list *sg);
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|
|
|
extern int opal_error_code(int rc);
|
|
|
|
ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
|
|
|
|
static inline int opal_get_async_rc(struct opal_msg msg)
|
|
{
|
|
if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
|
|
return OPAL_PARAMETER;
|
|
else
|
|
return be64_to_cpu(msg.params[1]);
|
|
}
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|
|
|
void opal_wake_poller(void);
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|
|
|
void opal_powercap_init(void);
|
|
void opal_psr_init(void);
|
|
void opal_sensor_groups_init(void);
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|
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_OPAL_H */
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