Ander Conselvan de Oliveira 89b3c3c7ee drm/i915/glk: Reuse broxton's cdclk code for GLK ... Geminilake has the same register layout, reference clock and programming sequence as broxton. The difference is that it doesn't support the 1.5 divider and has different ratios, but a lot of code can be shared between the two platforms. v2: Rebase (s/broxton/bxt). v3: Fix vco calculation in glk_de_pll_vco(). Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-7-git-send-email-ander.conselvan.de.oliveira@intel.com		2016-12-02 16:42:00 +02:00
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drm	drm/i915/glk: Reuse broxton's cdclk code for GLK	2016-12-02 16:42:00 +02:00
host1x	drm/tegra: dsi: Enhance runtime power management	2016-08-24 15:58:57 +02:00
ipu-v3	imx-drm plane update cleanup, YUV formats	2016-11-11 09:31:27 +10:00
vga	drivers/gpu/vga: allocate vga_arb_write() buffer on stack	2016-10-17 08:21:14 +02:00
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