mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 01:21:01 +07:00
bdfdabfedc
Dan Carpenter reports that we're passing a pointer to a pointer
here when we should just be passing a pointer. Pass the right
pointer so that the of_clk_hw_onecell_get() sees the appropriate
data pointer on its end.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: 9337631f52 ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
88 lines
3.3 KiB
C
88 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/efm32-cmu.h>
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#define CMU_HFPERCLKEN0 0x44
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#define CMU_MAX_CLKS 37
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static struct clk_hw_onecell_data *clk_data;
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static void __init efm32gg_cmu_init(struct device_node *np)
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{
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int i;
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void __iomem *base;
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struct clk_hw **hws;
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clk_data = kzalloc(sizeof(*clk_data) +
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sizeof(*clk_data->hws) * CMU_MAX_CLKS, GFP_KERNEL);
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if (!clk_data)
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return;
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hws = clk_data->hws;
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for (i = 0; i < CMU_MAX_CLKS; ++i)
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hws[i] = ERR_PTR(-ENOENT);
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("Failed to map address range for efm32gg,cmu node\n");
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return;
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}
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hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
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48000000);
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hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
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hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
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hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
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hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
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hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
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hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
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hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
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hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
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hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
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hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
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hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
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hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
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hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
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hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
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hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
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hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
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hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
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hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
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"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
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