mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 01:06:41 +07:00
44e4716499
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
324 lines
8.5 KiB
Plaintext
324 lines
8.5 KiB
Plaintext
/*
|
|
* Common support for CompuLab CM-T3x CoMs
|
|
*/
|
|
|
|
/ {
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x10000000>; /* 256 MB */
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&green_led_pins>;
|
|
ledb {
|
|
label = "cm-t3x:green";
|
|
gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */
|
|
linux,default-trigger = "heartbeat";
|
|
};
|
|
};
|
|
|
|
/* HS USB Port 1 Power */
|
|
hsusb1_power: hsusb1_power_reg {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "hsusb1_vbus";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
startup-delay-us = <70000>;
|
|
};
|
|
|
|
/* HS USB Port 2 Power */
|
|
hsusb2_power: hsusb2_power_reg {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "hsusb2_vbus";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
startup-delay-us = <70000>;
|
|
};
|
|
|
|
/* HS USB Host PHY on PORT 1 */
|
|
hsusb1_phy: hsusb1_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
vcc-supply = <&hsusb1_power>;
|
|
};
|
|
|
|
/* HS USB Host PHY on PORT 2 */
|
|
hsusb2_phy: hsusb2_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
vcc-supply = <&hsusb2_power>;
|
|
};
|
|
|
|
ads7846reg: ads7846-reg {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "ads7846-reg";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
tv0: connector@1 {
|
|
compatible = "svideo-connector";
|
|
label = "tv";
|
|
|
|
port {
|
|
tv_connector_in: endpoint {
|
|
remote-endpoint = <&venc_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&omap3_pmx_core {
|
|
|
|
uart3_pins: pinmux_uart3_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
|
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
|
|
>;
|
|
};
|
|
|
|
mmc1_pins: pinmux_mmc1_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
|
|
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
|
|
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
|
|
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
|
|
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
|
|
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
|
|
>;
|
|
};
|
|
|
|
green_led_pins: pinmux_green_led_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
|
|
>;
|
|
};
|
|
|
|
dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
|
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
|
|
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
|
|
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
|
|
|
|
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
|
|
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
|
|
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
|
|
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
|
|
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
|
|
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
|
|
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
|
|
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
|
|
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
|
|
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
|
|
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
|
|
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
|
|
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
|
|
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
|
|
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
|
|
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
|
|
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
|
|
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
|
>;
|
|
};
|
|
|
|
dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
|
|
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
|
|
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
|
|
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
|
|
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
|
|
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
|
|
>;
|
|
};
|
|
|
|
ads7846_pins: pinmux_ads7846_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
|
|
>;
|
|
};
|
|
|
|
mcspi1_pins: pinmux_mcspi1_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */
|
|
OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */
|
|
OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */
|
|
OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
|
|
>;
|
|
};
|
|
|
|
i2c1_pins: pinmux_i2c1_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
|
|
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
|
|
>;
|
|
};
|
|
|
|
mcbsp2_pins: pinmux_mcbsp2_pins {
|
|
pinctrl-single,pins = <
|
|
OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
|
|
OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
|
|
OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
|
|
OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_pins>;
|
|
};
|
|
|
|
&mmc1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
&mmc3 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&i2c1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
at24@50 {
|
|
compatible = "at24,24c02";
|
|
pagesize = <16>;
|
|
reg = <0x50>;
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&usbhshost {
|
|
port1-mode = "ehci-phy";
|
|
port2-mode = "ehci-phy";
|
|
};
|
|
|
|
&usbhsehci {
|
|
phys = <&hsusb1_phy &hsusb2_phy>;
|
|
};
|
|
|
|
&mcspi1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcspi1_pins>;
|
|
|
|
/* touch controller */
|
|
ads7846@0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ads7846_pins>;
|
|
|
|
compatible = "ti,ads7846";
|
|
vcc-supply = <&ads7846reg>;
|
|
|
|
reg = <0>; /* CS0 */
|
|
spi-max-frequency = <1500000>;
|
|
|
|
interrupt-parent = <&gpio2>;
|
|
interrupts = <25 0>; /* gpio_57 */
|
|
pendown-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
|
|
|
|
ti,x-min = /bits/ 16 <0x0>;
|
|
ti,x-max = /bits/ 16 <0x0fff>;
|
|
ti,y-min = /bits/ 16 <0x0>;
|
|
ti,y-max = /bits/ 16 <0x0fff>;
|
|
|
|
ti,x-plate-ohms = /bits/ 16 <180>;
|
|
ti,pressure-max = /bits/ 16 <255>;
|
|
|
|
ti,debounce-max = /bits/ 16 <30>;
|
|
ti,debounce-tol = /bits/ 16 <10>;
|
|
ti,debounce-rep = /bits/ 16 <1>;
|
|
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
&venc {
|
|
status = "ok";
|
|
|
|
port {
|
|
venc_out: endpoint {
|
|
remote-endpoint = <&tv_connector_in>;
|
|
ti,channels = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mcbsp2 {
|
|
status = "ok";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcbsp2_pins>;
|
|
};
|
|
|
|
&gpmc {
|
|
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
|
|
|
nand@0,0 {
|
|
compatible = "ti,omap2-nand";
|
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
interrupt-parent = <&gpmc>;
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
|
nand-bus-width = <8>;
|
|
gpmc,device-width = <1>;
|
|
ti,nand-ecc-opt = "sw";
|
|
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <120>;
|
|
gpmc,cs-wr-off-ns = <120>;
|
|
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <120>;
|
|
gpmc,adv-wr-off-ns = <120>;
|
|
|
|
gpmc,we-on-ns = <6>;
|
|
gpmc,we-off-ns = <90>;
|
|
|
|
gpmc,oe-on-ns = <6>;
|
|
gpmc,oe-off-ns = <90>;
|
|
|
|
gpmc,page-burst-access-ns = <6>;
|
|
gpmc,access-ns = <72>;
|
|
gpmc,cycle2cycle-delay-ns = <60>;
|
|
|
|
gpmc,rd-cycle-ns = <120>;
|
|
gpmc,wr-cycle-ns = <120>;
|
|
gpmc,wr-access-ns = <186>;
|
|
gpmc,wr-data-mux-bus-ns = <90>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "xloader";
|
|
reg = <0 0x80000>;
|
|
};
|
|
partition@0x80000 {
|
|
label = "uboot";
|
|
reg = <0x80000 0x1e0000>;
|
|
};
|
|
partition@0x260000 {
|
|
label = "uboot environment";
|
|
reg = <0x260000 0x40000>;
|
|
};
|
|
partition@0x2a0000 {
|
|
label = "linux";
|
|
reg = <0x2a0000 0x400000>;
|
|
};
|
|
partition@0x6a0000 {
|
|
label = "rootfs";
|
|
reg = <0x6a0000 0x1f880000>;
|
|
};
|
|
};
|
|
};
|