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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c01ce82941
Impact: cleanup Convert the last remaining users to struct irq_chip. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> CC: Mikael Starvik <starvik@axis.com> Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
264 lines
6.6 KiB
C
264 lines
6.6 KiB
C
/*
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* linux/arch/cris/kernel/irq.c
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*
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* Copyright (c) 2000-2002 Axis Communications AB
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*
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* Authors: Bjorn Wesen (bjornw@axis.com)
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*
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* This file contains the interrupt vectors and some
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* helper functions
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*
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*/
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#include <asm/irq.h>
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#include <asm/current.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
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#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
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/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
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* global just so that the kernel gdb can use it.
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*/
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void
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set_int_vector(int n, irqvectptr addr)
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{
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etrax_irv->v[n + 0x20] = (irqvectptr)addr;
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}
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/* the breakpoint vector is obviously not made just like the normal irq handlers
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* but needs to contain _code_ to jump to addr.
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*
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* the BREAK n instruction jumps to IBR + n * 8
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*/
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void
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set_break_vector(int n, irqvectptr addr)
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{
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unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2];
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unsigned long *jaddr = (unsigned long *)(jinstr + 1);
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/* if you don't know what this does, do not touch it! */
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*jinstr = 0x0d3f;
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*jaddr = (unsigned long)addr;
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/* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
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}
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/*
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* This builds up the IRQ handler stubs using some ugly macros in irq.h
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*
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* These macros create the low-level assembly IRQ routines that do all
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* the operations that are needed. They are also written to be fast - and to
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* disable interrupts as little as humanly possible.
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*
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*/
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/* IRQ0 and 1 are special traps */
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void hwbreakpoint(void);
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void IRQ1_interrupt(void);
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BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
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BUILD_IRQ(3, 0x08)
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BUILD_IRQ(4, 0x10)
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BUILD_IRQ(5, 0x20)
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BUILD_IRQ(6, 0x40)
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BUILD_IRQ(7, 0x80)
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BUILD_IRQ(8, 0x100)
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BUILD_IRQ(9, 0x200)
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BUILD_IRQ(10, 0x400)
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BUILD_IRQ(11, 0x800)
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BUILD_IRQ(12, 0x1000)
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BUILD_IRQ(13, 0x2000)
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void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
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void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
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BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */
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BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */
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BUILD_IRQ(18, 0x40000)
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BUILD_IRQ(19, 0x80000)
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BUILD_IRQ(20, 0x100000)
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BUILD_IRQ(21, 0x200000)
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BUILD_IRQ(22, 0x400000)
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BUILD_IRQ(23, 0x800000)
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BUILD_IRQ(24, 0x1000000)
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BUILD_IRQ(25, 0x2000000)
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/* IRQ 26-30 are reserved */
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BUILD_IRQ(31, 0x80000000)
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/*
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* Pointers to the low-level handlers
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*/
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static void (*interrupt[NR_IRQS])(void) = {
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NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
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IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
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IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
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IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
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IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
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IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
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IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
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IRQ31_interrupt
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};
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static void enable_crisv10_irq(unsigned int irq);
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static unsigned int startup_crisv10_irq(unsigned int irq)
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{
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enable_crisv10_irq(irq);
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return 0;
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}
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#define shutdown_crisv10_irq disable_crisv10_irq
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static void enable_crisv10_irq(unsigned int irq)
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{
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unmask_irq(irq);
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}
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static void disable_crisv10_irq(unsigned int irq)
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{
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mask_irq(irq);
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}
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static void ack_crisv10_irq(unsigned int irq)
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{
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}
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static void end_crisv10_irq(unsigned int irq)
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{
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}
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static struct irq_chip crisv10_irq_type = {
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.typename = "CRISv10",
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.startup = startup_crisv10_irq,
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.shutdown = shutdown_crisv10_irq,
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.enable = enable_crisv10_irq,
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.disable = disable_crisv10_irq,
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.ack = ack_crisv10_irq,
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.end = end_crisv10_irq,
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.set_affinity = NULL
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};
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void weird_irq(void);
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void system_call(void); /* from entry.S */
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void do_sigtrap(void); /* from entry.S */
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void gdb_handle_breakpoint(void); /* from entry.S */
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extern void do_IRQ(int irq, struct pt_regs * regs);
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/* Handle multiple IRQs */
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void do_multiple_IRQ(struct pt_regs* regs)
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{
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int bit;
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unsigned masked;
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unsigned mask;
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unsigned ethmask = 0;
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/* Get interrupts to mask and handle */
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mask = masked = *R_VECT_MASK_RD;
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/* Never mask timer IRQ */
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mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
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/*
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* If either ethernet interrupt (rx or tx) is active then block
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* the other one too. Unblock afterwards also.
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*/
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if (mask &
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(IO_STATE(R_VECT_MASK_RD, dma0, active) |
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IO_STATE(R_VECT_MASK_RD, dma1, active))) {
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ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
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IO_MASK(R_VECT_MASK_RD, dma1));
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}
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/* Block them */
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*R_VECT_MASK_CLR = (mask | ethmask);
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/* An extra irq_enter here to prevent softIRQs to run after
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* each do_IRQ. This will decrease the interrupt latency.
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*/
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irq_enter();
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/* Handle all IRQs */
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for (bit = 2; bit < 32; bit++) {
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if (masked & (1 << bit)) {
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do_IRQ(bit, regs);
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}
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}
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/* This irq_exit() will trigger the soft IRQs. */
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irq_exit();
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/* Unblock the IRQs again */
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*R_VECT_MASK_SET = (masked | ethmask);
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}
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/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
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setting the irq vector table.
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*/
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void __init
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init_IRQ(void)
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{
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int i;
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/* clear all interrupt masks */
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#ifndef CONFIG_SVINTO_SIM
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*R_IRQ_MASK0_CLR = 0xffffffff;
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*R_IRQ_MASK1_CLR = 0xffffffff;
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*R_IRQ_MASK2_CLR = 0xffffffff;
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#endif
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*R_VECT_MASK_CLR = 0xffffffff;
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for (i = 0; i < 256; i++)
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etrax_irv->v[i] = weird_irq;
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/* Initialize IRQ handler descriptors. */
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for(i = 2; i < NR_IRQS; i++) {
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irq_desc[i].chip = &crisv10_irq_type;
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set_int_vector(i, interrupt[i]);
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}
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/* the entries in the break vector contain actual code to be
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executed by the associated break handler, rather than just a jump
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address. therefore we need to setup a default breakpoint handler
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for all breakpoints */
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for (i = 0; i < 16; i++)
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set_break_vector(i, do_sigtrap);
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/* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
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set_int_vector(15, multiple_interrupt);
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/* 0 and 1 which are special breakpoint/NMI traps */
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set_int_vector(0, hwbreakpoint);
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set_int_vector(1, IRQ1_interrupt);
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/* and irq 14 which is the mmu bus fault handler */
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set_int_vector(14, mmu_bus_fault);
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/* setup the system-call trap, which is reached by BREAK 13 */
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set_break_vector(13, system_call);
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/* setup a breakpoint handler for debugging used for both user and
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kernel mode debugging (which is why it is not inside an ifdef
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CONFIG_ETRAX_KGDB) */
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set_break_vector(8, gdb_handle_breakpoint);
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#ifdef CONFIG_ETRAX_KGDB
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/* setup kgdb if its enabled, and break into the debugger */
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kgdb_init();
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breakpoint();
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#endif
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}
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