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88b333b0ed
Currently the value written to CP_RB_WPTR is calculated on the fly as (rb->next - rb->start). But as the code is designed rb->next is wrapped before writing the commands so if a series of commands happened to fit perfectly in the ringbuffer, rb->next would end up being equal to rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR. The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [squash in is_power_of_2() check] Signed-off-by: Rob Clark <robdclark@gmail.com> |
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| .. | ||
| a2xx.xml.h | ||
| a3xx_gpu.c | ||
| a3xx_gpu.h | ||
| a3xx.xml.h | ||
| a4xx_gpu.c | ||
| a4xx_gpu.h | ||
| a4xx.xml.h | ||
| a5xx_gpu.c | ||
| a5xx_gpu.h | ||
| a5xx_power.c | ||
| a5xx.xml.h | ||
| adreno_common.xml.h | ||
| adreno_device.c | ||
| adreno_gpu.c | ||
| adreno_gpu.h | ||
| adreno_pm4.xml.h | ||