mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 23:35:03 +07:00
f7df9be067
These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as well,
and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and
the Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition"
is added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7)
are supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported, which
in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet Processor",
following the IPQ806x that is used in many high-end WiFi routers. This one
integrates two ath10k wifi radios that were previously on separate chips.
Other boards that got added for existing chips are:
- On Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
- On Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
- On NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and
SoloX Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
- On Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
- On Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
- On Rockchips platform:
- mqmaker MiQi single-board computer
- On Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
- On Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC
single board computers
Across many platforms, bug fixes went in to address warnings that
dtc now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router),
Ti Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as
well, and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and the
Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition" is
added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7) are
supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported,
which in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet
Processor", following the IPQ806x that is used in many high-end WiFi
routers. This one integrates two ath10k wifi radios that were
previously on separate chips.
Other boards that got added for existing chips are:
Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and SoloX
Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
Rockchips platform:
- mqmaker MiQi single-board computer
Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC single board
computers
Across many platforms, bug fixes went in to address warnings that dtc
now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router), Ti
Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (458 commits)
ARM: dts: tango4: Import watchdog node
ARM: dts: tango4: Update cpus node for cpufreq
ARM: dts: tango4: Update DT to match clk driver
ARM: dts: tango4: Initial thermal support
arm/dst: Add Aspeed ast2500 device tree
arm/dts: Add Aspeed ast2400 device tree
ARM: sun7i: dt: Add pll3 and pll7 clocks
ARM: dts: sunxi: Add a olinuxino-lime2-emmc
ARM: dts: at91: sama5d4: add trng node
ARM: dts: at91: sama5d3: add trng node
ARM: dts: at91: sama5d2: add trng node
ARM: dts: at91: at91sam9g45 family: reduce the trng register map size
ARM: sun4i: dt: Add pll3 and pll7 clocks
ARM: sun5i: chip: Enable the TV Encoder
ARM: sun5i: r8: Add display blocks to the DTSI
ARM: sun5i: a13: Add display and TCON clocks
ARM: dts: ux500: configure the accelerometers open drain
ARM: mx5: dts: Enable USB OTG on M53EVK
ARM: dts: imx6ul-14x14-evk: Add audio support
ARM: dts: imx6qdl: Remove unneeded unit-addresses
...
1252 lines
29 KiB
Plaintext
1252 lines
29 KiB
Plaintext
/*
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* sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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model = "Atmel SAMA5D2 family SoC";
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compatible = "atmel,sama5d2";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart3;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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reg = <0x20000000 0x20000000>;
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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ns_sram: sram@00200000 {
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compatible = "mmio-sram";
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reg = <0x00200000 0x20000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb0: gadget@00300000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,sama5d3-udc";
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reg = <0x00300000 0x100000
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0xfc02c000 0x400>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&udphs_clk>, <&utmi>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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ep0 {
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reg = <0>;
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atmel,fifo-size = <64>;
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atmel,nb-banks = <1>;
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};
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ep1 {
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reg = <1>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep2 {
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reg = <2>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <3>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep3 {
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reg = <3>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep4 {
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reg = <4>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep5 {
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reg = <5>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep6 {
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reg = <6>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep7 {
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reg = <7>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-dma;
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atmel,can-isoc;
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};
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ep8 {
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reg = <8>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep9 {
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reg = <9>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep10 {
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reg = <10>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep11 {
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reg = <11>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep12 {
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reg = <12>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep13 {
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reg = <13>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep14 {
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reg = <14>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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ep15 {
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reg = <15>;
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atmel,fifo-size = <1024>;
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atmel,nb-banks = <2>;
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atmel,can-isoc;
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};
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};
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usb1: ohci@00400000 {
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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clock-names = "ohci_clk", "hclk", "uhpck";
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status = "disabled";
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};
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usb2: ehci@00500000 {
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compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
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reg = <0x00500000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&utmi>, <&uhphs_clk>;
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clock-names = "usb_clk", "ehci_clk";
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status = "disabled";
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};
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L2: cache-controller@00a00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a00000 0x1000>;
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interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
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cache-unified;
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cache-level = <2>;
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};
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nand0: nand@80000000 {
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compatible = "atmel,sama5d2-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = < /* EBI CS3 */
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0x80000000 0x08000000
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/* SMC PMECC regs */
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0xf8014070 0x00000490
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/* SMC PMECC Error Location regs */
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0xf8014500 0x00000200
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/* ROM Galois tables */
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0x00040000 0x00018000
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>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
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atmel,nand-addr-offset = <21>;
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atmel,nand-cmd-offset = <22>;
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atmel,nand-has-dma;
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atmel,has-pmecc;
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atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
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status = "disabled";
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nfc@c0000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < /* NFC Command Registers */
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0xc0000000 0x08000000
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/* NFC HSMC regs */
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0xf8014000 0x00000070
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/* NFC SRAM banks */
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0x00100000 0x00100000
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>;
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clocks = <&hsmc_clk>;
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atmel,write-by-sram;
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};
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};
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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sdmmc1: sdio-host@b0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xb0000000 0x300>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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|
#size-cells = <1>;
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ranges;
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|
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|
hlcdc: hlcdc@f0000000 {
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|
compatible = "atmel,sama5d2-hlcdc";
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reg = <0xf0000000 0x2000>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
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|
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
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|
clock-names = "periph_clk","sys_clk", "slow_clk";
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status = "disabled";
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|
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|
hlcdc-display-controller {
|
|
compatible = "atmel,hlcdc-display-controller";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
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|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
hlcdc_pwm: hlcdc-pwm {
|
|
compatible = "atmel,hlcdc-pwm";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
ramc0: ramc@f000c000 {
|
|
compatible = "atmel,sama5d3-ddramc";
|
|
reg = <0xf000c000 0x200>;
|
|
clocks = <&ddrck>, <&mpddr_clk>;
|
|
clock-names = "ddrck", "mpddr";
|
|
};
|
|
|
|
dma0: dma-controller@f0010000 {
|
|
compatible = "atmel,sama5d4-dma";
|
|
reg = <0xf0010000 0x1000>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
#dma-cells = <1>;
|
|
clocks = <&dma0_clk>;
|
|
clock-names = "dma_clk";
|
|
};
|
|
|
|
pmc: pmc@f0014000 {
|
|
compatible = "atmel,sama5d2-pmc", "syscon";
|
|
reg = <0xf0014000 0x160>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
|
|
main_rc_osc: main_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MOSCRCS>;
|
|
clock-frequency = <12000000>;
|
|
clock-accuracy = <100000000>;
|
|
};
|
|
|
|
main_osc: main_osc {
|
|
compatible = "atmel,at91rm9200-clk-main-osc";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MOSCS>;
|
|
clocks = <&main_xtal>;
|
|
};
|
|
|
|
main: mainck {
|
|
compatible = "atmel,at91sam9x5-clk-main";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MOSCSELS>;
|
|
clocks = <&main_rc_osc &main_osc>;
|
|
};
|
|
|
|
plla: pllack {
|
|
compatible = "atmel,sama5d3-clk-pll";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_LOCKA>;
|
|
clocks = <&main>;
|
|
reg = <0>;
|
|
atmel,clk-input-range = <12000000 12000000>;
|
|
#atmel,pll-clk-output-range-cells = <4>;
|
|
atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
|
|
};
|
|
|
|
plladiv: plladivck {
|
|
compatible = "atmel,at91sam9x5-clk-plldiv";
|
|
#clock-cells = <0>;
|
|
clocks = <&plla>;
|
|
};
|
|
|
|
utmi: utmick {
|
|
compatible = "atmel,at91sam9x5-clk-utmi";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_LOCKU>;
|
|
clocks = <&main>;
|
|
};
|
|
|
|
mck: masterck {
|
|
compatible = "atmel,at91sam9x5-clk-master";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MCKRDY>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
|
|
atmel,clk-output-range = <124000000 166000000>;
|
|
atmel,clk-divisors = <1 2 4 3>;
|
|
};
|
|
|
|
h32ck: h32mxck {
|
|
#clock-cells = <0>;
|
|
compatible = "atmel,sama5d4-clk-h32mx";
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
usb: usbck {
|
|
compatible = "atmel,at91sam9x5-clk-usb";
|
|
#clock-cells = <0>;
|
|
clocks = <&plladiv>, <&utmi>;
|
|
};
|
|
|
|
prog: progck {
|
|
compatible = "atmel,at91sam9x5-clk-programmable";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
prog0: prog0 {
|
|
#clock-cells = <0>;
|
|
reg = <0>;
|
|
interrupts = <AT91_PMC_PCKRDY(0)>;
|
|
};
|
|
|
|
prog1: prog1 {
|
|
#clock-cells = <0>;
|
|
reg = <1>;
|
|
interrupts = <AT91_PMC_PCKRDY(1)>;
|
|
};
|
|
|
|
prog2: prog2 {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
interrupts = <AT91_PMC_PCKRDY(2)>;
|
|
};
|
|
};
|
|
|
|
systemck {
|
|
compatible = "atmel,at91rm9200-clk-system";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ddrck: ddrck {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
lcdck: lcdck {
|
|
#clock-cells = <0>;
|
|
reg = <3>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
uhpck: uhpck {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
udpck: udpck {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
pck0: pck0 {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
clocks = <&prog0>;
|
|
};
|
|
|
|
pck1: pck1 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
clocks = <&prog1>;
|
|
};
|
|
|
|
pck2: pck2 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
clocks = <&prog2>;
|
|
};
|
|
|
|
iscck: iscck {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
clocks = <&mck>;
|
|
};
|
|
};
|
|
|
|
periph32ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&h32ck>;
|
|
|
|
macb0_clk: macb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <5>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tdes_clk: tdes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
matrix1_clk: matrix1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
};
|
|
|
|
hsmc_clk: hsmc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <17>;
|
|
};
|
|
|
|
pioA_clk: pioA_clk {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx0_clk: flx0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx1_clk: flx1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx2_clk: flx2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx3_clk: flx3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx4_clk: flx4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <23>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart0_clk: uart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart1_clk: uart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <25>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart2_clk: uart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <26>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart3_clk: uart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <27>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart4_clk: uart4_clk {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <29>;
|
|
#clock-cells = <0>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi1_clk: spi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <34>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_clk: tcb1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
adc_clk: adc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <40>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <41>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
trng_clk: trng_clk {
|
|
#clock-cells = <0>;
|
|
reg = <47>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_clk: pdmic_clk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s0_clk: i2s0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s1_clk: i2s1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
classd_clk: classd_clk {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
};
|
|
|
|
periph64ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
dma0_clk: dma0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
aes_clk: aes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
aesb_clk: aesb_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
sha_clk: sha_clk {
|
|
#clock-cells = <0>;
|
|
reg = <12>;
|
|
};
|
|
|
|
mpddr_clk: mpddr_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
matrix0_clk: matrix0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
};
|
|
|
|
sdmmc0_hclk: sdmmc0_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_hclk: sdmmc1_hclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
lcdc_clk: lcdc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
isc_clk: isc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <46>;
|
|
};
|
|
|
|
qspi0_clk: qspi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <52>;
|
|
};
|
|
|
|
qspi1_clk: qspi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <53>;
|
|
};
|
|
};
|
|
|
|
gck {
|
|
compatible = "atmel,sama5d2-clk-generated";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
sdmmc0_gclk: sdmmc0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
sdmmc1_gclk: sdmmc1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
tcb0_gclk: tcb0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_gclk: tcb1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_gclk: pwm_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_gclk: pdmic_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
|
|
i2s0_gclk: i2s0_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
i2s1_gclk: i2s1_gclk {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sha@f0028000 {
|
|
compatible = "atmel,at91sam9g46-sha";
|
|
reg = <0xf0028000 0x100>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(30))>;
|
|
dma-names = "tx";
|
|
clocks = <&sha_clk>;
|
|
clock-names = "sha_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
aes@f002c000 {
|
|
compatible = "atmel,at91sam9g46-aes";
|
|
reg = <0xf002c000 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(26))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(27))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&aes_clk>;
|
|
clock-names = "aes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(6))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(7))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "atmel,sama5d2-gem";
|
|
reg = <0xf8008000 0x1000>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
|
|
66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
|
|
67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f800c000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf800c000 0x100>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb0_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
tcb1: timer@f8010000 {
|
|
compatible = "atmel,at91sam9x5-tcb";
|
|
reg = <0xf8010000 0x100>;
|
|
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb1_clk>, <&clk32k>;
|
|
clock-names = "t0_clk", "slow_clk";
|
|
};
|
|
|
|
pdmic: pdmic@f8018000 {
|
|
compatible = "atmel,sama5d2-pdmic";
|
|
reg = <0xf8018000 0x124>;
|
|
interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
|
|
| AT91_XDMAC_DT_PERID(50))>;
|
|
dma-names = "rx";
|
|
clocks = <&pdmic_clk>, <&pdmic_gclk>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(35))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(36))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(37))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(38))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(39))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(40))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(0))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(1))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfr: sfr@f8030000 {
|
|
compatible = "atmel,sama5d2-sfr", "syscon";
|
|
reg = <0xf8030000 0x98>;
|
|
};
|
|
|
|
flx0: flexcom@f8034000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8034000 0x200>;
|
|
clocks = <&flx0_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8034000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx1: flexcom@f8038000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xf8038000 0x200>;
|
|
clocks = <&flx1_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf8038000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
shdwc@f8048010 {
|
|
compatible = "atmel,sama5d2-shdwc";
|
|
reg = <0xf8048010 0x10>;
|
|
clocks = <&clk32k>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,wakeup-rtc-timer;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
watchdog@f8048040 {
|
|
compatible = "atmel,sama5d4-wdt";
|
|
reg = <0xf8048040 0x10>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sckc@f8048050 {
|
|
compatible = "atmel,at91sam9x5-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
slow_rc_osc: slow_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-accuracy = <250000000>;
|
|
atmel,startup-time-usec = <75>;
|
|
};
|
|
|
|
slow_osc: slow_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_xtal>;
|
|
atmel,startup-time-usec = <1200000>;
|
|
};
|
|
|
|
clk32k: slowck {
|
|
compatible = "atmel,at91sam9x5-clk-slow";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_rc_osc &slow_osc>;
|
|
};
|
|
};
|
|
|
|
rtc@f80480b0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xf80480b0 0x30>;
|
|
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(8))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(9))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&spi1_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(41))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(42))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&uart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(43))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(44))>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&uart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
flx2: flexcom@fc010000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc010000 0x200>;
|
|
clocks = <&flx2_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc010000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx3: flexcom@fc014000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc014000 0x200>;
|
|
clocks = <&flx3_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc014000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx4: flexcom@fc018000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xfc018000 0x200>;
|
|
clocks = <&flx4_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xfc018000 0x800>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trng@fc01c000 {
|
|
compatible = "atmel,at91sam9g45-trng";
|
|
reg = <0xfc01c000 0x100>;
|
|
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&trng_clk>;
|
|
};
|
|
|
|
aic: interrupt-controller@fc020000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d2-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc020000 0x200>;
|
|
atmel,external-irqs = <49>;
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(2))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(3))>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@fc030000 {
|
|
compatible = "atmel,sama5d2-adc";
|
|
reg = <0xfc030000 0x100>;
|
|
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
clocks = <&adc_clk>;
|
|
clock-names = "adc_clk";
|
|
atmel,min-sample-rate-hz = <200000>;
|
|
atmel,max-sample-rate-hz = <20000000>;
|
|
atmel,startup-time-ms = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: pinctrl@fc038000 {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
reg = <0xfc038000 0x600>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<68 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<69 IRQ_TYPE_LEVEL_HIGH 7>,
|
|
<70 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
tdes@fc044000 {
|
|
compatible = "atmel,at91sam9g46-tdes";
|
|
reg = <0xfc044000 0x100>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
dmas = <&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(28))>,
|
|
<&dma0
|
|
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
|
|
AT91_XDMAC_DT_PERID(29))>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&tdes_clk>;
|
|
clock-names = "tdes_clk";
|
|
status = "okay";
|
|
};
|
|
|
|
chipid@fc069000 {
|
|
compatible = "atmel,sama5d2-chipid";
|
|
reg = <0xfc069000 0x8>;
|
|
};
|
|
};
|
|
};
|
|
};
|