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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d0bb1c1f4
Based on patches from Sonny Rao and Milton Miller... Combined the patches to fix up clean_tx_irq and clean_rx_irq. The PowerPC architecture does not require loads to independent bytes to be ordered without adding an explicit barrier. In ixgbe_clean_rx_irq we load the status bit then load the packet data. With packet split disabled if these loads go out of order we get a stale packet, but we will notice the bad sequence numbers and drop it. The problem occurs with packet split enabled where the TCP/IP header and data are in different descriptors. If the reads go out of order we may have data that doesn't match the TCP/IP header. Since we use hardware checksumming this bad data is never verified and it makes it all the way to the application. This bug was found during stress testing and adding this barrier has been shown to fix it. The bug can manifest as a data integrity issue (bad payload data) or as a BUG in skb_pull(). This was a nasty bug to hunt down, if people agree with the fix I think it's a candidate for stable. Previously Submitted to e1000-devel only for ixgbe http://marc.info/?l=e1000-devel&m=126593062701537&w=3 We've now seen this problem hit with other device drivers (e1000e mostly) So I'm resubmitting with fixes for other Intel Device Drivers with similar issues. CC: Milton Miller <miltonm@bga.com> CC: Anton Blanchard <anton@samba.org> CC: Sonny Rao <sonnyrao@us.ibm.com> CC: stable <stable@kernel.org> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| e1000_82575.c | ||
| e1000_82575.h | ||
| e1000_defines.h | ||
| e1000_hw.h | ||
| e1000_mac.c | ||
| e1000_mac.h | ||
| e1000_mbx.c | ||
| e1000_mbx.h | ||
| e1000_nvm.c | ||
| e1000_nvm.h | ||
| e1000_phy.c | ||
| e1000_phy.h | ||
| e1000_regs.h | ||
| igb_ethtool.c | ||
| igb_main.c | ||
| igb.h | ||
| Makefile | ||