Vineet Gupta 882a95ae0a ARC: make futex_atomic_cmpxchg_inatomic() return bimodal ... Callers of cmpxchg_futex_value_locked() in futex code expect bimodal return value: !0 (essentially -EFAULT as failure) 0 (success) Before this patch, the success return value was old value of futex, which could very well be non zero, causing caller to possibly take the failure path erroneously. Fix that by returning 0 for success (This fix was done back in 2011 for all upstream arches, which ARC obviously missed) Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Michel Lespinasse <walken@google.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-08-20 18:16:00 +05:30
..
arcregs.h	ARCv2: Support IO Coherency and permutations involving L1 and L2 caches	2015-08-20 18:11:17 +05:30
asm-offsets.h
atomic.h	ARCv2: spinlock/rwlock/atomics: reduce 1 instruction in exponential backoff	2015-08-07 13:56:16 +05:30
barrier.h	ARCv2: barriers	2015-06-25 06:00:17 +05:30
bitops.h	ARC: Make ARC bitops "safer" (add anti-optimization)	2015-07-09 17:36:32 +05:30
bug.h
cache.h	ARCv2: Support IO Coherency and permutations involving L1 and L2 caches	2015-08-20 18:11:17 +05:30
cacheflush.h	ARC: fold ___flush_dcache_page into __flush_dcache_page	2015-05-19 11:27:13 +05:30
checksum.h
clk.h
cmpxchg.h	ARC: add smp barriers around atomics per Documentation/atomic_ops.txt	2015-06-25 06:00:16 +05:30
current.h
delay.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
disasm.h
dma-mapping.h	Merge branch 'akpm' (patches from Andrew)	2015-07-01 17:47:51 -07:00
dma.h
elf.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-arcv2.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-compact.h	ARC: intc: split into ARCompact ISA specific, common bits	2015-06-19 18:09:40 +05:30
entry.h	ARCv2: STAR 9000808988: signals involving Delay Slot	2015-06-22 14:06:55 +05:30
exec.h
futex.h	ARC: make futex_atomic_cmpxchg_inatomic() return bimodal	2015-08-20 18:16:00 +05:30
io.h	- Support for HS38 cores based on ARCv2 ISA	2015-07-01 09:24:26 -07:00
irq.h	ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al	2015-06-22 14:06:56 +05:30
irqflags-arcv2.h	ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks	2015-06-22 14:06:55 +05:30
irqflags-compact.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
irqflags.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
Kbuild	mm: clean up per architecture MM hook header files	2015-07-17 16:39:53 -07:00
kdebug.h
kgdb.h
kprobes.h
linkage.h
mach_desc.h
mcip.h	ARCv2: SMP: clocksource: Enable Global Real Time counter	2015-06-22 14:06:57 +05:30
mmu_context.h
mmu.h	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
module.h
mutex.h
page.h
perf_event.h	ARC: perf: support cache hit/miss ratio	2015-04-20 18:27:34 +05:30
pgalloc.h
pgtable.h	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
processor.h	ARC: mm: document system mem map clearly	2015-06-19 18:09:29 +05:30
ptrace.h	ARC: Make pt_regs regs unsigned	2015-08-05 11:48:21 +05:30
sections.h
segment.h
serial.h	ARC: Dynamically determine BASE_BAUD from DeviceTree	2015-02-02 17:08:37 +05:30
setup.h
shmparam.h
smp.h
spinlock_types.h	ARC: LLOCK/SCOND based rwlock	2015-08-04 09:26:33 +05:30
spinlock.h	ARCv2: spinlock/rwlock/atomics: reduce 1 instruction in exponential backoff	2015-08-07 13:56:16 +05:30
stacktrace.h	ARC: Make arc_unwind_core accessible externally	2015-02-27 10:15:00 +05:30
string.h
switch_to.h
syscall.h
syscalls.h
thread_info.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
timex.h
tlb-mmu1.h
tlb.h
tlbflush.h
uaccess.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
unaligned.h
unwind.h