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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
277 lines
9.0 KiB
C
277 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/pgtable-3level.h
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*
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#ifndef _ASM_PGTABLE_3LEVEL_H
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#define _ASM_PGTABLE_3LEVEL_H
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/*
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* With LPAE, there are 3 levels of page tables. Each level has 512 entries of
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* 8 bytes each, occupying a 4K page. The first level table covers a range of
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* 512GB, each entry representing 1GB. Since we are limited to 4GB input
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* address range, only 4 entries in the PGD are used.
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*
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* There are enough spare bits in a page table entry for the kernel specific
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* state.
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*/
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#define PTRS_PER_PTE 512
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#define PTRS_PER_PMD 512
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#define PTRS_PER_PGD 4
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#define PTE_HWTABLE_PTRS (0)
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#define PTE_HWTABLE_OFF (0)
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#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map.
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*/
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#define PGDIR_SHIFT 30
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/*
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* PMD_SHIFT determines the size a middle-level page table entry can map.
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*/
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#define PMD_SHIFT 21
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~((1 << PMD_SHIFT) - 1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1))
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 21
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#define SECTION_SIZE (1UL << SECTION_SHIFT)
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#define SECTION_MASK (~((1 << SECTION_SHIFT) - 1))
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#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
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/*
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* Hugetlb definitions.
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*/
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#define HPAGE_SHIFT PMD_SHIFT
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#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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/*
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* "Linux" PTE definitions for LPAE.
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*
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* These bits overlap with the hardware bits but the naming is preserved for
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* consistency with the classic page table format.
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*/
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#define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
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#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
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#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
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#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
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#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55)
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#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56)
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#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
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#define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */
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#define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
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#define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
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#define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
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#define L_PMD_SECT_RDONLY (_AT(pteval_t, 1) << 58)
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/*
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* To be used in assembly code with the upper page attributes.
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*/
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#define L_PTE_XN_HIGH (1 << (54 - 32))
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#define L_PTE_DIRTY_HIGH (1 << (55 - 32))
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
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#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
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#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
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#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
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/*
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* Software PGD flags.
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*/
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#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
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/*
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* 2nd stage PTE definitions for LPAE.
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*/
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#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
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#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
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#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
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#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
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#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
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#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
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#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
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#define L_PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[1] */
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#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
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/*
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* Hyp-mode PL2 PTE definitions for LPAE.
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*/
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#define L_PTE_HYP L_PTE_USER
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#ifndef __ASSEMBLY__
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (!(pud_val(pud) & 2))
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#define pud_present(pud) (pud_val(pud))
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#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
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PMD_TYPE_TABLE)
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#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
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PMD_TYPE_SECT)
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#define pmd_large(pmd) pmd_sect(pmd)
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#define pud_clear(pudp) \
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do { \
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*pudp = __pud(0); \
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clean_pmd_entry(pudp); \
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} while (0)
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#define set_pud(pudp, pud) \
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do { \
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*pudp = pud; \
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flush_pmd_entry(pudp); \
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} while (0)
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static inline pmd_t *pud_page_vaddr(pud_t pud)
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{
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return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
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}
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/* Find an entry in the second-level page table.. */
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#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
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{
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return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
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}
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#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
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#define copy_pmd(pmdpd,pmdps) \
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do { \
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*pmdpd = *pmdps; \
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flush_pmd_entry(pmdpd); \
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} while (0)
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#define pmd_clear(pmdp) \
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do { \
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*pmdp = __pmd(0); \
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clean_pmd_entry(pmdp); \
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} while (0)
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/*
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* For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
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* that are written to a page table but not for ptes created with mk_pte.
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*
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* In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
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* hugetlb_cow, where it is compared with an entry in a page table.
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* This comparison test fails erroneously leading ultimately to a memory leak.
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*
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* To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
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* present before running the comparison.
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*/
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#define __HAVE_ARCH_PTE_SAME
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#define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
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: pte_val(pte_a)) \
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== (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
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: pte_val(pte_b)))
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#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
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#define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
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#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
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#define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \
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: !!(pmd_val(pmd) & (val)))
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#define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
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#define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
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#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
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#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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pte_val(pte) |= L_PTE_SPECIAL;
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return pte;
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}
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#define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
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#define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY))
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#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
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#define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
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#define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd))
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#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd))
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#endif
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#define PMD_BIT_FUNC(fn,op) \
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static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
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PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY);
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PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
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PMD_BIT_FUNC(mkwrite, &= ~L_PMD_SECT_RDONLY);
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PMD_BIT_FUNC(mkdirty, |= L_PMD_SECT_DIRTY);
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PMD_BIT_FUNC(mkclean, &= ~L_PMD_SECT_DIRTY);
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PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
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#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
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#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
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#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
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/* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */
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#define pmdp_establish generic_pmdp_establish
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/* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
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static inline pmd_t pmd_mknotpresent(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
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}
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static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
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{
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const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY |
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L_PMD_SECT_VALID | L_PMD_SECT_NONE;
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pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
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return pmd;
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}
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static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, pmd_t pmd)
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{
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BUG_ON(addr >= TASK_SIZE);
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/* create a faulting entry if PROT_NONE protected */
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if (pmd_val(pmd) & L_PMD_SECT_NONE)
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pmd_val(pmd) &= ~L_PMD_SECT_VALID;
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if (pmd_write(pmd) && pmd_dirty(pmd))
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pmd_val(pmd) &= ~PMD_SECT_AP2;
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else
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pmd_val(pmd) |= PMD_SECT_AP2;
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*pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
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flush_pmd_entry(pmdp);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_PGTABLE_3LEVEL_H */
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