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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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61b5c1587d
After GPU reset, GuC HW needs to be reinitialized (with FW reload).
Unfortunately, we're doing some extra work there (mostly allocating stuff),
work that can be moved to guc_init and called once at driver load time.
As a side effect we're no longer hitting an assert in
i915_ggtt_enable_guc on suspend/resume.
v2: Do not duplicate disable_communication / reset_guc_interrupts
v3: Add proper teardown after rebase
References: 04f7b24ecc
("drm/i915/guc: Assert that we switch between known ggtt->invalidate functions")
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171213221352.7173-3-michal.winiarski@intel.com
384 lines
9.3 KiB
C
384 lines
9.3 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_uc.h"
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#include "intel_guc_submission.h"
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#include "intel_guc.h"
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#include "i915_drv.h"
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/* Reset GuC providing us with fresh state for both GuC and HuC.
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*/
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static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 guc_status;
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ret = intel_reset_guc(dev_priv);
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if (ret) {
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DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
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return ret;
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}
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guc_status = I915_READ(GUC_STATUS);
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WARN(!(guc_status & GS_MIA_IN_RESET),
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"GuC status: 0x%x, MIA core expected to be in reset\n",
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guc_status);
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return ret;
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}
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static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
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{
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struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
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struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
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int enable_guc = 0;
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/* Default is to enable GuC/HuC if we know their firmwares */
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if (intel_uc_fw_is_selected(guc_fw))
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enable_guc |= ENABLE_GUC_SUBMISSION;
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if (intel_uc_fw_is_selected(huc_fw))
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enable_guc |= ENABLE_GUC_LOAD_HUC;
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/* Any platform specific fine-tuning can be done here */
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return enable_guc;
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}
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/**
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* intel_uc_sanitize_options - sanitize uC related modparam options
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* @dev_priv: device private
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*
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* In case of "enable_guc" option this function will attempt to modify
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* it only if it was initially set to "auto(-1)". Default value for this
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* modparam varies between platforms and it is hardcoded in driver code.
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* Any other modparam value is only monitored against availability of the
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* related hardware or firmware definitions.
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*/
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void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
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{
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struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
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struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
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/* A negative value means "use platform default" */
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if (i915_modparams.enable_guc < 0)
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i915_modparams.enable_guc = __get_platform_enable_guc(dev_priv);
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DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
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i915_modparams.enable_guc,
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yesno(intel_uc_is_using_guc_submission()),
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yesno(intel_uc_is_using_huc()));
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/* Verify GuC firmware availability */
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if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
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DRM_WARN("Incompatible option detected: enable_guc=%d, %s!\n",
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i915_modparams.enable_guc,
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!HAS_GUC(dev_priv) ? "no GuC hardware" :
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"no GuC firmware");
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}
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/* Verify HuC firmware availability */
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if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
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DRM_WARN("Incompatible option detected: enable_guc=%d, %s!\n",
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i915_modparams.enable_guc,
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!HAS_HUC(dev_priv) ? "no HuC hardware" :
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"no HuC firmware");
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}
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/* Make sure that sanitization was done */
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GEM_BUG_ON(i915_modparams.enable_guc < 0);
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}
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void intel_uc_init_early(struct drm_i915_private *dev_priv)
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{
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intel_guc_init_early(&dev_priv->guc);
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intel_huc_init_early(&dev_priv->huc);
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}
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void intel_uc_init_fw(struct drm_i915_private *dev_priv)
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{
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if (!USES_GUC(dev_priv))
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return;
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if (USES_HUC(dev_priv))
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intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw);
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intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw);
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}
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void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
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{
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if (!USES_GUC(dev_priv))
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return;
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intel_uc_fw_fini(&dev_priv->guc.fw);
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if (USES_HUC(dev_priv))
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intel_uc_fw_fini(&dev_priv->huc.fw);
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}
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/**
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* intel_uc_init_mmio - setup uC MMIO access
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*
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* @dev_priv: device private
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*
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* Setup minimal state necessary for MMIO accesses later in the
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* initialization sequence.
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*/
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void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
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{
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intel_guc_init_send_regs(&dev_priv->guc);
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}
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static void guc_capture_load_err_log(struct intel_guc *guc)
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{
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if (!guc->log.vma || i915_modparams.guc_log_level < 0)
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return;
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if (!guc->load_err_log)
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guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
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return;
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}
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static void guc_free_load_err_log(struct intel_guc *guc)
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{
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if (guc->load_err_log)
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i915_gem_object_put(guc->load_err_log);
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}
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static int guc_enable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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if (HAS_GUC_CT(dev_priv))
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return intel_guc_enable_ct(guc);
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guc->send = intel_guc_send_mmio;
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return 0;
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}
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static void guc_disable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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if (HAS_GUC_CT(dev_priv))
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intel_guc_disable_ct(guc);
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guc->send = intel_guc_send_nop;
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}
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int intel_uc_init_wq(struct drm_i915_private *dev_priv)
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{
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int ret;
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if (!USES_GUC(dev_priv))
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return 0;
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ret = intel_guc_init_wq(&dev_priv->guc);
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if (ret) {
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DRM_ERROR("Couldn't allocate workqueues for GuC\n");
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return ret;
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}
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return 0;
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}
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void intel_uc_fini_wq(struct drm_i915_private *dev_priv)
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{
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if (!USES_GUC(dev_priv))
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return;
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GEM_BUG_ON(!HAS_GUC(dev_priv));
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intel_guc_fini_wq(&dev_priv->guc);
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}
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int intel_uc_init(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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int ret;
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if (!USES_GUC(dev_priv))
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return 0;
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if (!HAS_GUC(dev_priv))
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return -ENODEV;
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ret = intel_guc_init(guc);
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if (ret)
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return ret;
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if (USES_GUC_SUBMISSION(dev_priv)) {
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/*
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* This is stuff we need to have available at fw load time
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* if we are planning to enable submission later
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*/
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ret = intel_guc_submission_init(guc);
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if (ret) {
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intel_guc_fini(guc);
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return ret;
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}
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}
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return 0;
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}
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void intel_uc_fini(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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if (!USES_GUC(dev_priv))
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return;
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GEM_BUG_ON(!HAS_GUC(dev_priv));
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if (USES_GUC_SUBMISSION(dev_priv))
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intel_guc_submission_fini(guc);
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intel_guc_fini(guc);
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}
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int intel_uc_init_hw(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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struct intel_huc *huc = &dev_priv->huc;
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int ret, attempts;
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if (!USES_GUC(dev_priv))
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return 0;
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GEM_BUG_ON(!HAS_GUC(dev_priv));
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guc_disable_communication(guc);
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gen9_reset_guc_interrupts(dev_priv);
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/* init WOPCM */
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I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
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I915_WRITE(DMA_GUC_WOPCM_OFFSET,
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GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
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/* WaEnableuKernelHeaderValidFix:skl */
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/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
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if (IS_GEN9(dev_priv))
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attempts = 3;
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else
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attempts = 1;
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while (attempts--) {
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/*
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* Always reset the GuC just before (re)loading, so
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* that the state and timing are fairly predictable
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*/
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ret = __intel_uc_reset_hw(dev_priv);
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if (ret)
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goto err_out;
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if (USES_HUC(dev_priv)) {
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ret = intel_huc_init_hw(huc);
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if (ret)
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goto err_out;
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}
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intel_guc_init_params(guc);
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ret = intel_guc_fw_upload(guc);
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if (ret == 0 || ret != -EAGAIN)
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break;
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DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
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"retry %d more time(s)\n", ret, attempts);
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}
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/* Did we succeded or run out of retries? */
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if (ret)
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goto err_log_capture;
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ret = guc_enable_communication(guc);
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if (ret)
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goto err_log_capture;
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if (USES_HUC(dev_priv)) {
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ret = intel_huc_auth(huc);
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if (ret)
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goto err_communication;
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}
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if (USES_GUC_SUBMISSION(dev_priv)) {
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if (i915_modparams.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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ret = intel_guc_submission_enable(guc);
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if (ret)
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goto err_interrupts;
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}
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dev_info(dev_priv->drm.dev, "GuC firmware version %u.%u\n",
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guc->fw.major_ver_found, guc->fw.minor_ver_found);
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dev_info(dev_priv->drm.dev, "GuC submission %s\n",
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enableddisabled(USES_GUC_SUBMISSION(dev_priv)));
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dev_info(dev_priv->drm.dev, "HuC %s\n",
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enableddisabled(USES_HUC(dev_priv)));
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return 0;
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/*
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* We've failed to load the firmware :(
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*/
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err_interrupts:
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gen9_disable_guc_interrupts(dev_priv);
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err_communication:
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guc_disable_communication(guc);
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err_log_capture:
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guc_capture_load_err_log(guc);
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err_out:
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/*
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* Note that there is no fallback as either user explicitly asked for
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* the GuC or driver default option was to run with the GuC enabled.
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*/
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if (GEM_WARN_ON(ret == -EIO))
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ret = -EINVAL;
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dev_err(dev_priv->drm.dev, "GuC initialization failed %d\n", ret);
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return ret;
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}
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void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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guc_free_load_err_log(guc);
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if (!USES_GUC(dev_priv))
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return;
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GEM_BUG_ON(!HAS_GUC(dev_priv));
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if (USES_GUC_SUBMISSION(dev_priv))
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intel_guc_submission_disable(guc);
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guc_disable_communication(guc);
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if (USES_GUC_SUBMISSION(dev_priv))
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gen9_disable_guc_interrupts(dev_priv);
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}
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