mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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87e90c76e0
Allow evicting all BOs from the GTT domain. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
804 lines
19 KiB
C
804 lines
19 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/kthread.h>
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#include <drm/drmP.h>
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#include <linux/debugfs.h>
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#include "amdgpu.h"
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/*
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* Debugfs
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*/
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int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
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const struct drm_info_list *files,
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unsigned nfiles)
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{
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unsigned i;
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for (i = 0; i < adev->debugfs_count; i++) {
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if (adev->debugfs[i].files == files) {
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/* Already registered */
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return 0;
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}
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}
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i = adev->debugfs_count + 1;
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if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
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DRM_ERROR("Reached maximum number of debugfs components.\n");
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DRM_ERROR("Report so we increase "
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"AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
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return -EINVAL;
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}
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adev->debugfs[adev->debugfs_count].files = files;
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adev->debugfs[adev->debugfs_count].num_files = nfiles;
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adev->debugfs_count = i;
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#if defined(CONFIG_DEBUG_FS)
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drm_debugfs_create_files(files, nfiles,
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adev->ddev->primary->debugfs_root,
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adev->ddev->primary);
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#endif
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return 0;
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}
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#if defined(CONFIG_DEBUG_FS)
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static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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bool pm_pg_lock, use_bank;
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unsigned instance_bank, sh_bank, se_bank;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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/* are we reading registers for which a PG lock is necessary? */
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pm_pg_lock = (*pos >> 23) & 1;
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if (*pos & (1ULL << 62)) {
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se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
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sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
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instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
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if (se_bank == 0x3FF)
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se_bank = 0xFFFFFFFF;
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if (sh_bank == 0x3FF)
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sh_bank = 0xFFFFFFFF;
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if (instance_bank == 0x3FF)
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instance_bank = 0xFFFFFFFF;
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use_bank = 1;
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} else {
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use_bank = 0;
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}
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*pos &= (1UL << 22) - 1;
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if (use_bank) {
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if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
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(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
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return -EINVAL;
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mutex_lock(&adev->grbm_idx_mutex);
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amdgpu_gfx_select_se_sh(adev, se_bank,
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sh_bank, instance_bank);
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}
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if (pm_pg_lock)
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mutex_lock(&adev->pm.mutex);
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while (size) {
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uint32_t value;
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if (*pos > adev->rmmio_size)
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goto end;
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value = RREG32(*pos >> 2);
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r = put_user(value, (uint32_t *)buf);
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if (r) {
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result = r;
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goto end;
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}
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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end:
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if (use_bank) {
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amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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if (pm_pg_lock)
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mutex_unlock(&adev->pm.mutex);
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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bool pm_pg_lock, use_bank;
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unsigned instance_bank, sh_bank, se_bank;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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/* are we reading registers for which a PG lock is necessary? */
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pm_pg_lock = (*pos >> 23) & 1;
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if (*pos & (1ULL << 62)) {
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se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
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sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
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instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
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if (se_bank == 0x3FF)
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se_bank = 0xFFFFFFFF;
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if (sh_bank == 0x3FF)
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sh_bank = 0xFFFFFFFF;
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if (instance_bank == 0x3FF)
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instance_bank = 0xFFFFFFFF;
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use_bank = 1;
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} else {
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use_bank = 0;
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}
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*pos &= (1UL << 22) - 1;
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if (use_bank) {
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if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
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(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
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return -EINVAL;
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mutex_lock(&adev->grbm_idx_mutex);
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amdgpu_gfx_select_se_sh(adev, se_bank,
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sh_bank, instance_bank);
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}
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if (pm_pg_lock)
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mutex_lock(&adev->pm.mutex);
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while (size) {
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uint32_t value;
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if (*pos > adev->rmmio_size)
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return result;
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r = get_user(value, (uint32_t *)buf);
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if (r)
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return r;
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WREG32(*pos >> 2, value);
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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if (use_bank) {
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amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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if (pm_pg_lock)
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mutex_unlock(&adev->pm.mutex);
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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value = RREG32_PCIE(*pos >> 2);
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r = put_user(value, (uint32_t *)buf);
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if (r)
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return r;
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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r = get_user(value, (uint32_t *)buf);
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if (r)
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return r;
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WREG32_PCIE(*pos >> 2, value);
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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value = RREG32_DIDT(*pos >> 2);
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r = put_user(value, (uint32_t *)buf);
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if (r)
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return r;
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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r = get_user(value, (uint32_t *)buf);
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if (r)
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return r;
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WREG32_DIDT(*pos >> 2, value);
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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value = RREG32_SMC(*pos);
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r = put_user(value, (uint32_t *)buf);
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if (r)
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return r;
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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while (size) {
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uint32_t value;
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r = get_user(value, (uint32_t *)buf);
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if (r)
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return r;
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WREG32_SMC(*pos, value);
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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return result;
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}
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static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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ssize_t result = 0;
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int r;
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uint32_t *config, no_regs = 0;
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
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if (!config)
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return -ENOMEM;
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/* version, increment each time something is added */
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config[no_regs++] = 3;
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config[no_regs++] = adev->gfx.config.max_shader_engines;
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config[no_regs++] = adev->gfx.config.max_tile_pipes;
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config[no_regs++] = adev->gfx.config.max_cu_per_sh;
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config[no_regs++] = adev->gfx.config.max_sh_per_se;
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config[no_regs++] = adev->gfx.config.max_backends_per_se;
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config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
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config[no_regs++] = adev->gfx.config.max_gprs;
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config[no_regs++] = adev->gfx.config.max_gs_threads;
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config[no_regs++] = adev->gfx.config.max_hw_contexts;
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config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
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config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
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config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
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config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
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config[no_regs++] = adev->gfx.config.num_tile_pipes;
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config[no_regs++] = adev->gfx.config.backend_enable_mask;
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config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
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config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
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config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
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config[no_regs++] = adev->gfx.config.num_gpus;
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config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
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config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
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config[no_regs++] = adev->gfx.config.gb_addr_config;
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config[no_regs++] = adev->gfx.config.num_rbs;
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/* rev==1 */
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config[no_regs++] = adev->rev_id;
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config[no_regs++] = adev->pg_flags;
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config[no_regs++] = adev->cg_flags;
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/* rev==2 */
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config[no_regs++] = adev->family;
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config[no_regs++] = adev->external_rev_id;
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/* rev==3 */
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config[no_regs++] = adev->pdev->device;
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config[no_regs++] = adev->pdev->revision;
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config[no_regs++] = adev->pdev->subsystem_device;
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config[no_regs++] = adev->pdev->subsystem_vendor;
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while (size && (*pos < no_regs * 4)) {
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uint32_t value;
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value = config[*pos >> 2];
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r = put_user(value, (uint32_t *)buf);
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if (r) {
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kfree(config);
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return r;
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}
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result += 4;
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buf += 4;
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*pos += 4;
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size -= 4;
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}
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kfree(config);
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return result;
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}
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static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = file_inode(f)->i_private;
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int idx, x, outsize, r, valuesize;
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uint32_t values[16];
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if (size & 3 || *pos & 0x3)
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return -EINVAL;
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if (amdgpu_dpm == 0)
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return -EINVAL;
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/* convert offset to sensor number */
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idx = *pos >> 2;
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valuesize = sizeof(values);
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if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
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r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
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else
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return -EINVAL;
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if (size > valuesize)
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return -EINVAL;
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outsize = 0;
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x = 0;
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if (!r) {
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while (size) {
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r = put_user(values[x++], (int32_t *)buf);
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buf += 4;
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size -= 4;
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outsize += 4;
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}
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}
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return !r ? outsize : r;
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}
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static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_device *adev = f->f_inode->i_private;
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int r, x;
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ssize_t result=0;
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uint32_t offset, se, sh, cu, wave, simd, data[32];
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if (size & 3 || *pos & 3)
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return -EINVAL;
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/* decode offset */
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offset = (*pos & GENMASK_ULL(6, 0));
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se = (*pos & GENMASK_ULL(14, 7)) >> 7;
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sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
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cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
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wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
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simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
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|
|
/* switch to the specific se/sh/cu */
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
amdgpu_gfx_select_se_sh(adev, se, sh, cu);
|
|
|
|
x = 0;
|
|
if (adev->gfx.funcs->read_wave_data)
|
|
adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
|
|
|
|
amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
if (!x)
|
|
return -EINVAL;
|
|
|
|
while (size && (offset < x * 4)) {
|
|
uint32_t value;
|
|
|
|
value = data[offset >> 2];
|
|
r = put_user(value, (uint32_t *)buf);
|
|
if (r)
|
|
return r;
|
|
|
|
result += 4;
|
|
buf += 4;
|
|
offset += 4;
|
|
size -= 4;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
|
|
size_t size, loff_t *pos)
|
|
{
|
|
struct amdgpu_device *adev = f->f_inode->i_private;
|
|
int r;
|
|
ssize_t result = 0;
|
|
uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
|
|
|
|
if (size & 3 || *pos & 3)
|
|
return -EINVAL;
|
|
|
|
/* decode offset */
|
|
offset = *pos & GENMASK_ULL(11, 0);
|
|
se = (*pos & GENMASK_ULL(19, 12)) >> 12;
|
|
sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
|
|
cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
|
|
wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
|
|
simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
|
|
thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
|
|
bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
|
|
|
|
data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
/* switch to the specific se/sh/cu */
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
amdgpu_gfx_select_se_sh(adev, se, sh, cu);
|
|
|
|
if (bank == 0) {
|
|
if (adev->gfx.funcs->read_wave_vgprs)
|
|
adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
|
|
} else {
|
|
if (adev->gfx.funcs->read_wave_sgprs)
|
|
adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
|
|
}
|
|
|
|
amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
while (size) {
|
|
uint32_t value;
|
|
|
|
value = data[offset++];
|
|
r = put_user(value, (uint32_t *)buf);
|
|
if (r) {
|
|
result = r;
|
|
goto err;
|
|
}
|
|
|
|
result += 4;
|
|
buf += 4;
|
|
size -= 4;
|
|
}
|
|
|
|
err:
|
|
kfree(data);
|
|
return result;
|
|
}
|
|
|
|
static const struct file_operations amdgpu_debugfs_regs_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_regs_read,
|
|
.write = amdgpu_debugfs_regs_write,
|
|
.llseek = default_llseek
|
|
};
|
|
static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_regs_didt_read,
|
|
.write = amdgpu_debugfs_regs_didt_write,
|
|
.llseek = default_llseek
|
|
};
|
|
static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_regs_pcie_read,
|
|
.write = amdgpu_debugfs_regs_pcie_write,
|
|
.llseek = default_llseek
|
|
};
|
|
static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_regs_smc_read,
|
|
.write = amdgpu_debugfs_regs_smc_write,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
static const struct file_operations amdgpu_debugfs_gca_config_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_gca_config_read,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
static const struct file_operations amdgpu_debugfs_sensors_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_sensor_read,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
static const struct file_operations amdgpu_debugfs_wave_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_wave_read,
|
|
.llseek = default_llseek
|
|
};
|
|
static const struct file_operations amdgpu_debugfs_gpr_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = amdgpu_debugfs_gpr_read,
|
|
.llseek = default_llseek
|
|
};
|
|
|
|
static const struct file_operations *debugfs_regs[] = {
|
|
&amdgpu_debugfs_regs_fops,
|
|
&amdgpu_debugfs_regs_didt_fops,
|
|
&amdgpu_debugfs_regs_pcie_fops,
|
|
&amdgpu_debugfs_regs_smc_fops,
|
|
&amdgpu_debugfs_gca_config_fops,
|
|
&amdgpu_debugfs_sensors_fops,
|
|
&amdgpu_debugfs_wave_fops,
|
|
&amdgpu_debugfs_gpr_fops,
|
|
};
|
|
|
|
static const char *debugfs_regs_names[] = {
|
|
"amdgpu_regs",
|
|
"amdgpu_regs_didt",
|
|
"amdgpu_regs_pcie",
|
|
"amdgpu_regs_smc",
|
|
"amdgpu_gca_config",
|
|
"amdgpu_sensors",
|
|
"amdgpu_wave",
|
|
"amdgpu_gpr",
|
|
};
|
|
|
|
int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
|
|
{
|
|
struct drm_minor *minor = adev->ddev->primary;
|
|
struct dentry *ent, *root = minor->debugfs_root;
|
|
unsigned i, j;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
|
|
ent = debugfs_create_file(debugfs_regs_names[i],
|
|
S_IFREG | S_IRUGO, root,
|
|
adev, debugfs_regs[i]);
|
|
if (IS_ERR(ent)) {
|
|
for (j = 0; j < i; j++) {
|
|
debugfs_remove(adev->debugfs_regs[i]);
|
|
adev->debugfs_regs[i] = NULL;
|
|
}
|
|
return PTR_ERR(ent);
|
|
}
|
|
|
|
if (!i)
|
|
i_size_write(ent->d_inode, adev->rmmio_size);
|
|
adev->debugfs_regs[i] = ent;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
|
|
{
|
|
unsigned i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
|
|
if (adev->debugfs_regs[i]) {
|
|
debugfs_remove(adev->debugfs_regs[i]);
|
|
adev->debugfs_regs[i] = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
int r = 0, i;
|
|
|
|
/* hold on the scheduler */
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
if (!ring || !ring->sched.thread)
|
|
continue;
|
|
kthread_park(ring->sched.thread);
|
|
}
|
|
|
|
seq_printf(m, "run ib test:\n");
|
|
r = amdgpu_ib_ring_tests(adev);
|
|
if (r)
|
|
seq_printf(m, "ib ring tests failed (%d).\n", r);
|
|
else
|
|
seq_printf(m, "ib ring tests passed.\n");
|
|
|
|
/* go on the scheduler */
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
|
|
if (!ring || !ring->sched.thread)
|
|
continue;
|
|
kthread_unpark(ring->sched.thread);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
seq_write(m, adev->bios, adev->bios_size);
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT));
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_info_list amdgpu_debugfs_list[] = {
|
|
{"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
|
|
{"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
|
|
{"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram},
|
|
{"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt},
|
|
};
|
|
|
|
int amdgpu_debugfs_init(struct amdgpu_device *adev)
|
|
{
|
|
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
|
|
ARRAY_SIZE(amdgpu_debugfs_list));
|
|
}
|
|
|
|
#else
|
|
int amdgpu_debugfs_init(struct amdgpu_device *adev)
|
|
{
|
|
return 0;
|
|
}
|
|
int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
|
|
{
|
|
return 0;
|
|
}
|
|
void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
|
|
#endif
|