mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 11:06:39 +07:00
117a2cc38f
Commit f77d55a3b5 ("serial: 8250_dw: get index of serial line from DT
aliases") made the serial driver now use the serial aliases to get the tty
number, pointing out that our aliases have been wrong all along.
Remove them from the DTSI and add custom ones in the relevant boards.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
800 lines
19 KiB
Plaintext
800 lines
19 KiB
Plaintext
/*
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* Copyright 2012 Stefan Roese
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* Stefan Roese <sr@denx.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&intc>;
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aliases {
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ethernet0 = &emac;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
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<&ahb_gates 44>;
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status = "disabled";
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};
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framebuffer@1 {
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compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
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allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
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<&ahb_gates 44>, <&ahb_gates 46>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll4";
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};
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pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll5-clk";
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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axi_gates: clk@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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clock-output-names = "ahb";
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};
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ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
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"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
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"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
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"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
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"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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clock-output-names = "apb0";
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};
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apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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apb1: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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clock-output-names = "apb1";
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};
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apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can", "apb1_scr",
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"apb1_ps20", "apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20098 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ts";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi2";
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};
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pata_clk: clk@01c200ac {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "pata";
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};
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ir0_clk: clk@01c200b0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200b0 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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ir1_clk: clk@01c200b4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200b4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir1";
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};
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usb_clk: clk@01c200cc {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun4i-a10-usb-clk";
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reg = <0x01c200cc 0x4>;
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clocks = <&pll6 1>;
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clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
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};
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spi3_clk: clk@01c200d4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200d4 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi3";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <27>;
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clocks = <&ahb_gates 6>;
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#dma-cells = <2>;
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};
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spi0: spi@01c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <10>;
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clocks = <&ahb_gates 20>, <&spi0_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 1 27>, <&dma 1 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@01c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <11>;
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clocks = <&ahb_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 1 9>, <&dma 1 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <55>;
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clocks = <&ahb_gates 17>;
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status = "disabled";
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};
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mdio@01c0b080 {
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compatible = "allwinner,sun4i-a10-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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interrupts = <32>;
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status = "disabled";
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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interrupts = <33>;
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status = "disabled";
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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interrupts = <34>;
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status = "disabled";
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};
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mmc3: mmc@01c12000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ahb_gates 11>, <&mmc3_clk>;
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clock-names = "ahb", "mmc";
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interrupts = <35>;
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status = "disabled";
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};
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usbphy: phy@01c13400 {
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#phy-cells = <1>;
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compatible = "allwinner,sun4i-a10-usb-phy";
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reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
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reg-names = "phy_ctrl", "pmu1", "pmu2";
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clocks = <&usb_clk 8>;
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clock-names = "usb_phy";
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resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
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reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
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status = "disabled";
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};
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ehci0: usb@01c14000 {
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compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
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reg = <0x01c14000 0x100>;
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interrupts = <39>;
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clocks = <&ahb_gates 1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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|
|
|
ohci0: usb@01c14400 {
|
|
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
|
reg = <0x01c14400 0x100>;
|
|
interrupts = <64>;
|
|
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@01c17000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c17000 0x1000>;
|
|
interrupts = <12>;
|
|
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 1 29>, <&dma 1 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
ahci: sata@01c18000 {
|
|
compatible = "allwinner,sun4i-a10-ahci";
|
|
reg = <0x01c18000 0x1000>;
|
|
interrupts = <56>;
|
|
clocks = <&pll6 0>, <&ahb_gates 25>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@01c1c000 {
|
|
compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
|
|
reg = <0x01c1c000 0x100>;
|
|
interrupts = <40>;
|
|
clocks = <&ahb_gates 3>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@01c1c400 {
|
|
compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
|
|
reg = <0x01c1c400 0x100>;
|
|
interrupts = <65>;
|
|
clocks = <&usb_clk 7>, <&ahb_gates 4>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@01c1f000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c1f000 0x1000>;
|
|
interrupts = <50>;
|
|
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 1 31>, <&dma 1 30>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
intc: interrupt-controller@01c20400 {
|
|
compatible = "allwinner,sun4i-a10-ic";
|
|
reg = <0x01c20400 0x400>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun4i-a10-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <28>;
|
|
clocks = <&apb0_gates 5>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
pwm0_pins_a: pwm0@0 {
|
|
allwinner,pins = "PB2";
|
|
allwinner,function = "pwm";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
pwm1_pins_a: pwm1@0 {
|
|
allwinner,pins = "PI3";
|
|
allwinner,function = "pwm";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PB22", "PB23";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
uart0_pins_b: uart0@1 {
|
|
allwinner,pins = "PF2", "PF4";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
uart1_pins_a: uart1@0 {
|
|
allwinner,pins = "PA10", "PA11";
|
|
allwinner,function = "uart1";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
allwinner,pins = "PB0", "PB1";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
allwinner,pins = "PB18", "PB19";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
allwinner,pins = "PB20", "PB21";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
emac_pins_a: emac0@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
allwinner,function = "emac";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <2>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
|
|
allwinner,pins = "PH1";
|
|
allwinner,function = "gpio_in";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <1>;
|
|
};
|
|
|
|
ir0_pins_a: ir0@0 {
|
|
allwinner,pins = "PB3","PB4";
|
|
allwinner,function = "ir0";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
|
|
ir1_pins_a: ir1@0 {
|
|
allwinner,pins = "PB22","PB23";
|
|
allwinner,function = "ir1";
|
|
allwinner,drive = <0>;
|
|
allwinner,pull = <0>;
|
|
};
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <22>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt: watchdog@01c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
};
|
|
|
|
rtc: rtc@01c20d00 {
|
|
compatible = "allwinner,sun4i-a10-rtc";
|
|
reg = <0x01c20d00 0x20>;
|
|
interrupts = <24>;
|
|
};
|
|
|
|
pwm: pwm@01c20e00 {
|
|
compatible = "allwinner,sun4i-a10-pwm";
|
|
reg = <0x01c20e00 0xc>;
|
|
clocks = <&osc24M>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir0: ir@01c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <5>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir1: ir@01c21c00 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&apb0_gates 7>, <&ir1_clk>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <6>;
|
|
reg = <0x01c21c00 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sid: eeprom@01c23800 {
|
|
compatible = "allwinner,sun4i-a10-sid";
|
|
reg = <0x01c23800 0x10>;
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun4i-a10-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <29>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <1>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <2>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <3>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <4>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <17>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <18>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@01c29800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29800 0x400>;
|
|
interrupts = <19>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@01c29c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29c00 0x400>;
|
|
interrupts = <20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb1_gates 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <7>;
|
|
clocks = <&apb1_gates 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <8>;
|
|
clocks = <&apb1_gates 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <9>;
|
|
clocks = <&apb1_gates 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|