mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 11:36:41 +07:00
876e7fb9f4
Enable the DU device and the VGA port available on the r8a7794 ALT board. The VGA portion of the ALT board is somewhat similar to the Lager board but in case of ALT the DU1 pins are used and the X2 clock has a reduced frequency. This patch does not include any pinctrl (PFC) settings due to lack of PFC DT integration on r8a7794. At this point the default state of the boot loader is enough to keep the VGA port working without changing any pinctrl settings. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
123 lines
1.9 KiB
Plaintext
123 lines
1.9 KiB
Plaintext
/*
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* Device Tree Source for the Alt board
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7794.dtsi"
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/ {
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model = "Alt";
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compatible = "renesas,alt", "renesas,r8a7794";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = &scif2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb1>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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x2_clk: x2-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <74250000>;
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};
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x13_clk: x13-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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};
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&du {
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status = "okay";
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clocks = <&mstp7_clks R8A7794_CLK_DU0>,
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<&mstp7_clks R8A7794_CLK_DU0>,
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<&x13_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
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ports {
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port@1 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&cmt0 {
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status = "okay";
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};
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ðer {
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc0>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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};
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};
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&scif2 {
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status = "okay";
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};
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