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484367b6a9
This patch includes the atomic and futex operations. Many atomic operations use the load-lock word(llw) and store-condition word(scw) operations. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
16 lines
428 B
C
16 lines
428 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#ifndef __NDS32_ASM_BARRIER_H
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#define __NDS32_ASM_BARRIER_H
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#ifndef __ASSEMBLY__
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#define mb() asm volatile("msync all":::"memory")
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#define rmb() asm volatile("msync all":::"memory")
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#define wmb() asm volatile("msync store":::"memory")
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __NDS32_ASM_BARRIER_H */
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