mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 20:06:41 +07:00
42452b77a1
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Dirk Teurlings <dirk@upexia.nl> Tested-by: Peter van Valderen <p.v.valderen@gmail.com>
174 lines
4.2 KiB
C
174 lines
4.2 KiB
C
/*
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* arch/arm/mach-orion5x/wrt350n-v2-setup.c
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/delay.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mv643xx_eth.h>
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#include <asm/mach-types.h>
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#include <asm/gpio.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <asm/arch/orion5x.h>
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#include "common.h"
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#include "mpp.h"
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static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
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{ 0, MPP_GPIO }, /* Power LED green (0=on) */
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{ 1, MPP_GPIO }, /* Security LED (0=on) */
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{ 2, MPP_GPIO }, /* Internal Button (0=on) */
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{ 3, MPP_GPIO }, /* Reset Button (0=on) */
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{ 4, MPP_GPIO }, /* PCI int */
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{ 5, MPP_GPIO }, /* Power LED orange (0=on) */
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{ 6, MPP_GPIO }, /* USB LED (0=on) */
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{ 7, MPP_GPIO }, /* Wireless LED (0=on) */
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{ 8, MPP_UNUSED }, /* ??? */
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{ 9, MPP_GIGE }, /* GE_RXERR */
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{ 10, MPP_UNUSED }, /* ??? */
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{ 11, MPP_UNUSED }, /* ??? */
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{ 12, MPP_GIGE }, /* GE_TXD[4] */
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{ 13, MPP_GIGE }, /* GE_TXD[5] */
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{ 14, MPP_GIGE }, /* GE_TXD[6] */
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{ 15, MPP_GIGE }, /* GE_TXD[7] */
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{ 16, MPP_GIGE }, /* GE_RXD[4] */
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{ 17, MPP_GIGE }, /* GE_RXD[5] */
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{ 18, MPP_GIGE }, /* GE_RXD[6] */
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{ 19, MPP_GIGE }, /* GE_RXD[7] */
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{ -1 },
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};
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/*
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* 8M NOR flash Device bus boot chip select
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*/
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#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000
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#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M
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static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
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{
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.name = "kernel",
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.offset = 0x00000000,
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.size = 0x00760000,
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}, {
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.name = "rootfs",
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.offset = 0x001a0000,
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.size = 0x005c0000,
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}, {
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.name = "lang",
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.offset = 0x00760000,
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.size = 0x00040000,
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}, {
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.name = "nvram",
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.offset = 0x007a0000,
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.size = 0x00020000,
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}, {
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.name = "u-boot",
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.offset = 0x007c0000,
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.size = 0x00040000,
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},
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};
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static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
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.width = 1,
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.parts = wrt350n_v2_nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
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};
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static struct resource wrt350n_v2_nor_flash_resource = {
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.flags = IORESOURCE_MEM,
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.start = WRT350N_V2_NOR_BOOT_BASE,
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.end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
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};
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static struct platform_device wrt350n_v2_nor_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &wrt350n_v2_nor_flash_data,
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},
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.num_resources = 1,
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.resource = &wrt350n_v2_nor_flash_resource,
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};
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static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
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.phy_addr = -1,
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};
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static void __init wrt350n_v2_init(void)
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{
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/*
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* Setup basic Orion functions. Need to be called early.
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*/
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orion5x_init();
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orion5x_mpp_conf(wrt350n_v2_mpp_modes);
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/*
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* Configure peripherals.
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*/
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orion5x_ehci0_init();
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orion5x_eth_init(&wrt350n_v2_eth_data);
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orion5x_uart0_init();
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orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
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WRT350N_V2_NOR_BOOT_SIZE);
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platform_device_register(&wrt350n_v2_nor_flash);
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}
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static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* Mini-PCI slot.
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*/
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if (slot == 7)
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return gpio_to_irq(4);
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return -1;
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}
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static struct hw_pci wrt350n_v2_pci __initdata = {
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.nr_controllers = 2,
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.swizzle = pci_std_swizzle,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = wrt350n_v2_pci_map_irq,
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};
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static int __init wrt350n_v2_pci_init(void)
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{
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if (machine_is_wrt350n_v2())
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pci_common_init(&wrt350n_v2_pci);
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return 0;
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}
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subsys_initcall(wrt350n_v2_pci_init);
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MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
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/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
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.phys_io = ORION5X_REGS_PHYS_BASE,
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.io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
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.boot_params = 0x00000100,
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.init_machine = wrt350n_v2_init,
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.map_io = orion5x_map_io,
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.init_irq = orion5x_init_irq,
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.timer = &orion5x_timer,
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.fixup = tag_fixup_mem32,
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MACHINE_END
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