mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 01:13:55 +07:00
7c4541a37b
Before we return control to the system, and letting it reuse all the pages being accessed by HW, we must disable the HW. At the moment, we dare not reset the GPU if it will clobber the display, but once we know the display has been disabled, we can proceed with the reset as we shutdown the module. We know the next user must reinitialise the HW for their purpose. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/489 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200525151459.12083-1-chris@chris-wilson.co.uk
645 lines
15 KiB
C
645 lines
15 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "debugfs_gt.h"
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#include "i915_drv.h"
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#include "intel_context.h"
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#include "intel_gt.h"
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#include "intel_gt_buffer_pool.h"
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#include "intel_gt_clock_utils.h"
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#include "intel_gt_pm.h"
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#include "intel_gt_requests.h"
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#include "intel_mocs.h"
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#include "intel_rc6.h"
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#include "intel_renderstate.h"
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#include "intel_rps.h"
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#include "intel_uncore.h"
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#include "intel_pm.h"
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#include "shmem_utils.h"
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void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
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{
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gt->i915 = i915;
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gt->uncore = &i915->uncore;
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spin_lock_init(>->irq_lock);
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INIT_LIST_HEAD(>->closed_vma);
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spin_lock_init(>->closed_lock);
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intel_gt_init_buffer_pool(gt);
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intel_gt_init_reset(gt);
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intel_gt_init_requests(gt);
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intel_gt_init_timelines(gt);
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intel_gt_pm_init_early(gt);
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intel_rps_init_early(>->rps);
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intel_uc_init_early(>->uc);
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}
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void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
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{
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gt->ggtt = ggtt;
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}
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static void init_unused_ring(struct intel_gt *gt, u32 base)
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{
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struct intel_uncore *uncore = gt->uncore;
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intel_uncore_write(uncore, RING_CTL(base), 0);
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intel_uncore_write(uncore, RING_HEAD(base), 0);
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intel_uncore_write(uncore, RING_TAIL(base), 0);
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intel_uncore_write(uncore, RING_START(base), 0);
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}
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static void init_unused_rings(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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if (IS_I830(i915)) {
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init_unused_ring(gt, PRB1_BASE);
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init_unused_ring(gt, SRB0_BASE);
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init_unused_ring(gt, SRB1_BASE);
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init_unused_ring(gt, SRB2_BASE);
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init_unused_ring(gt, SRB3_BASE);
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} else if (IS_GEN(i915, 2)) {
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init_unused_ring(gt, SRB0_BASE);
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init_unused_ring(gt, SRB1_BASE);
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} else if (IS_GEN(i915, 3)) {
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init_unused_ring(gt, PRB1_BASE);
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init_unused_ring(gt, PRB2_BASE);
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}
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}
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int intel_gt_init_hw(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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int ret;
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gt->last_init_time = ktime_get();
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/* Double layer security blanket, see i915_gem_init() */
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
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intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
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if (IS_HASWELL(i915))
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intel_uncore_write(uncore,
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MI_PREDICATE_RESULT_2,
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IS_HSW_GT3(i915) ?
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LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
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/* Apply the GT workarounds... */
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intel_gt_apply_workarounds(gt);
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/* ...and determine whether they are sticking. */
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intel_gt_verify_workarounds(gt, "init");
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intel_gt_init_swizzling(gt);
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/*
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* At least 830 can leave some of the unused rings
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* "active" (ie. head != tail) after resume which
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* will prevent c3 entry. Makes sure all unused rings
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* are totally idle.
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*/
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init_unused_rings(gt);
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ret = i915_ppgtt_init_hw(gt);
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if (ret) {
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DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
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goto out;
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}
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/* We can't enable contexts until all firmware is loaded */
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ret = intel_uc_init_hw(>->uc);
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if (ret) {
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i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
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goto out;
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}
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intel_mocs_init(gt);
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out:
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intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
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return ret;
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}
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static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
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{
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intel_uncore_rmw(uncore, reg, 0, set);
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}
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static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
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{
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intel_uncore_rmw(uncore, reg, clr, 0);
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}
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static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
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{
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intel_uncore_rmw(uncore, reg, 0, 0);
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}
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static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
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{
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GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
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GEN6_RING_FAULT_REG_POSTING_READ(engine);
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}
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void
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intel_gt_clear_error_registers(struct intel_gt *gt,
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intel_engine_mask_t engine_mask)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct intel_uncore *uncore = gt->uncore;
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u32 eir;
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if (!IS_GEN(i915, 2))
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clear_register(uncore, PGTBL_ER);
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if (INTEL_GEN(i915) < 4)
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clear_register(uncore, IPEIR(RENDER_RING_BASE));
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else
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clear_register(uncore, IPEIR_I965);
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clear_register(uncore, EIR);
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eir = intel_uncore_read(uncore, EIR);
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if (eir) {
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/*
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* some errors might have become stuck,
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* mask them.
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*/
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DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
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rmw_set(uncore, EMR, eir);
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intel_uncore_write(uncore, GEN2_IIR,
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I915_MASTER_ERROR_INTERRUPT);
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}
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if (INTEL_GEN(i915) >= 12) {
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rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
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intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
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} else if (INTEL_GEN(i915) >= 8) {
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rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
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intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
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} else if (INTEL_GEN(i915) >= 6) {
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine_masked(engine, gt, engine_mask, id)
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gen8_clear_engine_error_register(engine);
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}
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}
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static void gen6_check_faults(struct intel_gt *gt)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 fault;
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for_each_engine(engine, gt, id) {
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fault = GEN6_RING_FAULT_REG_READ(engine);
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if (fault & RING_FAULT_VALID) {
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drm_dbg(&engine->i915->drm, "Unexpected fault\n"
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"\tAddr: 0x%08lx\n"
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"\tAddress space: %s\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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fault & PAGE_MASK,
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fault & RING_FAULT_GTTSEL_MASK ?
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"GGTT" : "PPGTT",
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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}
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static void gen8_check_faults(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
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u32 fault;
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if (INTEL_GEN(gt->i915) >= 12) {
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fault_reg = GEN12_RING_FAULT_REG;
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fault_data0_reg = GEN12_FAULT_TLB_DATA0;
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fault_data1_reg = GEN12_FAULT_TLB_DATA1;
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} else {
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fault_reg = GEN8_RING_FAULT_REG;
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fault_data0_reg = GEN8_FAULT_TLB_DATA0;
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fault_data1_reg = GEN8_FAULT_TLB_DATA1;
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}
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fault = intel_uncore_read(uncore, fault_reg);
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if (fault & RING_FAULT_VALID) {
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u32 fault_data0, fault_data1;
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u64 fault_addr;
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fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
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fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
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fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
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((u64)fault_data0 << 12);
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drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
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"\tAddr: 0x%08x_%08x\n"
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"\tAddress space: %s\n"
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"\tEngine ID: %d\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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upper_32_bits(fault_addr), lower_32_bits(fault_addr),
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fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
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GEN8_RING_FAULT_ENGINE_ID(fault),
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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void intel_gt_check_and_clear_faults(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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/* From GEN8 onwards we only have one 'All Engine Fault Register' */
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if (INTEL_GEN(i915) >= 8)
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gen8_check_faults(gt);
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else if (INTEL_GEN(i915) >= 6)
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gen6_check_faults(gt);
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else
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return;
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intel_gt_clear_error_registers(gt, ALL_ENGINES);
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}
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void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
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{
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struct intel_uncore *uncore = gt->uncore;
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intel_wakeref_t wakeref;
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/*
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* No actual flushing is required for the GTT write domain for reads
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* from the GTT domain. Writes to it "immediately" go to main memory
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* as far as we know, so there's no chipset flush. It also doesn't
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* land in the GPU render cache.
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*
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* However, we do have to enforce the order so that all writes through
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* the GTT land before any writes to the device, such as updates to
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* the GATT itself.
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*
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* We also have to wait a bit for the writes to land from the GTT.
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* An uncached read (i.e. mmio) seems to be ideal for the round-trip
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* timing. This issue has only been observed when switching quickly
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* between GTT writes and CPU reads from inside the kernel on recent hw,
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* and it appears to only affect discrete GTT blocks (i.e. on LLC
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* system agents we cannot reproduce this behaviour, until Cannonlake
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* that was!).
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*/
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wmb();
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if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
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return;
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intel_gt_chipset_flush(gt);
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with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
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unsigned long flags;
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spin_lock_irqsave(&uncore->lock, flags);
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intel_uncore_posting_read_fw(uncore,
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RING_HEAD(RENDER_RING_BASE));
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spin_unlock_irqrestore(&uncore->lock, flags);
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}
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}
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void intel_gt_chipset_flush(struct intel_gt *gt)
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{
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wmb();
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if (INTEL_GEN(gt->i915) < 6)
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intel_gtt_chipset_flush();
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}
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void intel_gt_driver_register(struct intel_gt *gt)
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{
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intel_rps_driver_register(>->rps);
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debugfs_gt_register(gt);
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}
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static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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obj = i915_gem_object_create_stolen(i915, size);
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if (IS_ERR(obj))
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obj = i915_gem_object_create_internal(i915, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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return PTR_ERR(obj);
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}
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_ggtt_pin(vma, 0, PIN_HIGH);
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if (ret)
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goto err_unref;
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gt->scratch = i915_vma_make_unshrinkable(vma);
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return 0;
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err_unref:
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i915_gem_object_put(obj);
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return ret;
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}
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static void intel_gt_fini_scratch(struct intel_gt *gt)
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{
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i915_vma_unpin_and_release(>->scratch, 0);
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}
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static struct i915_address_space *kernel_vm(struct intel_gt *gt)
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{
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if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
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return &i915_ppgtt_create(gt)->vm;
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else
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return i915_vm_get(>->ggtt->vm);
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}
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static int __engines_record_defaults(struct intel_gt *gt)
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{
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struct i915_request *requests[I915_NUM_ENGINES] = {};
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int err = 0;
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/*
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* As we reset the gpu during very early sanitisation, the current
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* register state on the GPU should reflect its defaults values.
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* We load a context onto the hw (with restore-inhibit), then switch
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* over to a second context to save that default register state. We
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* can then prime every new context with that state so they all start
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* from the same default HW values.
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*/
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for_each_engine(engine, gt, id) {
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struct intel_renderstate so;
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struct intel_context *ce;
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struct i915_request *rq;
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/* We must be able to switch to something! */
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GEM_BUG_ON(!engine->kernel_context);
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err = intel_renderstate_init(&so, engine);
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if (err)
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goto out;
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ce = intel_context_create(engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto out;
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}
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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intel_context_put(ce);
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goto out;
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}
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err = intel_engine_emit_ctx_wa(rq);
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if (err)
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goto err_rq;
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err = intel_renderstate_emit(&so, rq);
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if (err)
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goto err_rq;
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err_rq:
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requests[id] = i915_request_get(rq);
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i915_request_add(rq);
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intel_renderstate_fini(&so);
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if (err)
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goto out;
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}
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/* Flush the default context image to memory, and enable powersaving. */
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if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
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err = -EIO;
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goto out;
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}
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for (id = 0; id < ARRAY_SIZE(requests); id++) {
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struct i915_request *rq;
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struct file *state;
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rq = requests[id];
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if (!rq)
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continue;
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if (rq->fence.error) {
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err = -EIO;
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goto out;
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}
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GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
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if (!rq->context->state)
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continue;
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/* Keep a copy of the state's backing pages; free the obj */
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state = shmem_create_from_object(rq->context->state->obj);
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if (IS_ERR(state)) {
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err = PTR_ERR(state);
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goto out;
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}
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rq->engine->default_state = state;
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}
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out:
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/*
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* If we have to abandon now, we expect the engines to be idle
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* and ready to be torn-down. The quickest way we can accomplish
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* this is by declaring ourselves wedged.
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*/
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if (err)
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intel_gt_set_wedged(gt);
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for (id = 0; id < ARRAY_SIZE(requests); id++) {
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struct intel_context *ce;
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struct i915_request *rq;
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rq = requests[id];
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if (!rq)
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continue;
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ce = rq->context;
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i915_request_put(rq);
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intel_context_put(ce);
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}
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return err;
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|
}
|
|
|
|
static int __engines_verify_workarounds(struct intel_gt *gt)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
int err = 0;
|
|
|
|
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
|
|
return 0;
|
|
|
|
for_each_engine(engine, gt, id) {
|
|
if (intel_engine_verify_workarounds(engine, "load"))
|
|
err = -EIO;
|
|
}
|
|
|
|
/* Flush and restore the kernel context for safety */
|
|
if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
|
|
err = -EIO;
|
|
|
|
return err;
|
|
}
|
|
|
|
static void __intel_gt_disable(struct intel_gt *gt)
|
|
{
|
|
intel_gt_set_wedged_on_init(gt);
|
|
|
|
intel_gt_suspend_prepare(gt);
|
|
intel_gt_suspend_late(gt);
|
|
|
|
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
|
|
}
|
|
|
|
int intel_gt_init(struct intel_gt *gt)
|
|
{
|
|
int err;
|
|
|
|
err = i915_inject_probe_error(gt->i915, -ENODEV);
|
|
if (err)
|
|
return err;
|
|
|
|
/*
|
|
* This is just a security blanket to placate dragons.
|
|
* On some systems, we very sporadically observe that the first TLBs
|
|
* used by the CS may be stale, despite us poking the TLB reset. If
|
|
* we hold the forcewake during initialisation these problems
|
|
* just magically go away.
|
|
*/
|
|
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
|
|
|
|
intel_gt_init_clock_frequency(gt);
|
|
|
|
err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
|
|
if (err)
|
|
goto out_fw;
|
|
|
|
intel_gt_pm_init(gt);
|
|
|
|
gt->vm = kernel_vm(gt);
|
|
if (!gt->vm) {
|
|
err = -ENOMEM;
|
|
goto err_pm;
|
|
}
|
|
|
|
err = intel_engines_init(gt);
|
|
if (err)
|
|
goto err_engines;
|
|
|
|
err = intel_uc_init(>->uc);
|
|
if (err)
|
|
goto err_engines;
|
|
|
|
err = intel_gt_resume(gt);
|
|
if (err)
|
|
goto err_uc_init;
|
|
|
|
err = __engines_record_defaults(gt);
|
|
if (err)
|
|
goto err_gt;
|
|
|
|
err = __engines_verify_workarounds(gt);
|
|
if (err)
|
|
goto err_gt;
|
|
|
|
err = i915_inject_probe_error(gt->i915, -EIO);
|
|
if (err)
|
|
goto err_gt;
|
|
|
|
goto out_fw;
|
|
err_gt:
|
|
__intel_gt_disable(gt);
|
|
intel_uc_fini_hw(>->uc);
|
|
err_uc_init:
|
|
intel_uc_fini(>->uc);
|
|
err_engines:
|
|
intel_engines_release(gt);
|
|
i915_vm_put(fetch_and_zero(>->vm));
|
|
err_pm:
|
|
intel_gt_pm_fini(gt);
|
|
intel_gt_fini_scratch(gt);
|
|
out_fw:
|
|
if (err)
|
|
intel_gt_set_wedged_on_init(gt);
|
|
intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
|
|
return err;
|
|
}
|
|
|
|
void intel_gt_driver_remove(struct intel_gt *gt)
|
|
{
|
|
__intel_gt_disable(gt);
|
|
|
|
intel_uc_driver_remove(>->uc);
|
|
|
|
intel_engines_release(gt);
|
|
}
|
|
|
|
void intel_gt_driver_unregister(struct intel_gt *gt)
|
|
{
|
|
intel_rps_driver_unregister(>->rps);
|
|
|
|
/*
|
|
* Upon unregistering the device to prevent any new users, cancel
|
|
* all in-flight requests so that we can quickly unbind the active
|
|
* resources.
|
|
*/
|
|
intel_gt_set_wedged(gt);
|
|
}
|
|
|
|
void intel_gt_driver_release(struct intel_gt *gt)
|
|
{
|
|
struct i915_address_space *vm;
|
|
intel_wakeref_t wakeref;
|
|
|
|
/* Scrub all HW state upon release */
|
|
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
|
|
__intel_gt_reset(gt, ALL_ENGINES);
|
|
|
|
vm = fetch_and_zero(>->vm);
|
|
if (vm) /* FIXME being called twice on error paths :( */
|
|
i915_vm_put(vm);
|
|
|
|
intel_gt_pm_fini(gt);
|
|
intel_gt_fini_scratch(gt);
|
|
intel_gt_fini_buffer_pool(gt);
|
|
}
|
|
|
|
void intel_gt_driver_late_release(struct intel_gt *gt)
|
|
{
|
|
/* We need to wait for inflight RCU frees to release their grip */
|
|
rcu_barrier();
|
|
|
|
intel_uc_driver_late_release(>->uc);
|
|
intel_gt_fini_requests(gt);
|
|
intel_gt_fini_reset(gt);
|
|
intel_gt_fini_timelines(gt);
|
|
intel_engines_free(gt);
|
|
}
|