mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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693ffc0802
The first invocation of storage key operations on a given cpu will be intercepted. On these intercepts we will enable storage keys for the guest and remove the previously added intercepts. Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* S390 version
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*
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* Derived from "include/asm-i386/mmu_context.h"
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*/
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#ifndef __S390_MMU_CONTEXT_H
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#define __S390_MMU_CONTEXT_H
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#include <asm/pgalloc.h>
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#include <asm/uaccess.h>
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#include <asm/tlbflush.h>
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#include <asm/ctl_reg.h>
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static inline int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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cpumask_clear(&mm->context.cpu_attach_mask);
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atomic_set(&mm->context.attach_count, 0);
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mm->context.flush_mm = 0;
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mm->context.asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
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#ifdef CONFIG_64BIT
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mm->context.asce_bits |= _ASCE_TYPE_REGION3;
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#endif
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mm->context.has_pgste = 0;
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mm->context.use_skey = 0;
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mm->context.asce_limit = STACK_TOP_MAX;
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crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
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return 0;
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}
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#define destroy_context(mm) do { } while (0)
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static inline void update_user_asce(struct mm_struct *mm, int load_primary)
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{
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pgd_t *pgd = mm->pgd;
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S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
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if (load_primary)
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__ctl_load(S390_lowcore.user_asce, 1, 1);
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set_fs(current->thread.mm_segment);
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}
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static inline void clear_user_asce(struct mm_struct *mm, int load_primary)
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{
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S390_lowcore.user_asce = S390_lowcore.kernel_asce;
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if (load_primary)
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__ctl_load(S390_lowcore.user_asce, 1, 1);
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__ctl_load(S390_lowcore.user_asce, 7, 7);
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}
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static inline void update_primary_asce(struct task_struct *tsk)
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{
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unsigned long asce;
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__ctl_store(asce, 1, 1);
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if (asce != S390_lowcore.kernel_asce)
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__ctl_load(S390_lowcore.kernel_asce, 1, 1);
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set_tsk_thread_flag(tsk, TIF_ASCE);
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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int cpu = smp_processor_id();
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update_primary_asce(tsk);
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if (prev == next)
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return;
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if (MACHINE_HAS_TLB_LC)
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cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
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if (atomic_inc_return(&next->context.attach_count) >> 16) {
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/* Delay update_user_asce until all TLB flushes are done. */
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set_tsk_thread_flag(tsk, TIF_TLB_WAIT);
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/* Clear old ASCE by loading the kernel ASCE. */
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clear_user_asce(next, 0);
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} else {
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cpumask_set_cpu(cpu, mm_cpumask(next));
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update_user_asce(next, 0);
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if (next->context.flush_mm)
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/* Flush pending TLBs */
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__tlb_flush_mm(next);
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}
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atomic_dec(&prev->context.attach_count);
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WARN_ON(atomic_read(&prev->context.attach_count) < 0);
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if (MACHINE_HAS_TLB_LC)
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cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
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}
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#define finish_arch_post_lock_switch finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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struct task_struct *tsk = current;
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struct mm_struct *mm = tsk->mm;
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if (!test_tsk_thread_flag(tsk, TIF_TLB_WAIT))
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return;
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preempt_disable();
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clear_tsk_thread_flag(tsk, TIF_TLB_WAIT);
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while (atomic_read(&mm->context.attach_count) >> 16)
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cpu_relax();
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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update_user_asce(mm, 0);
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if (mm->context.flush_mm)
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__tlb_flush_mm(mm);
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preempt_enable();
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}
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#define enter_lazy_tlb(mm,tsk) do { } while (0)
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#define deactivate_mm(tsk,mm) do { } while (0)
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static inline void activate_mm(struct mm_struct *prev,
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struct mm_struct *next)
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{
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switch_mm(prev, next, current);
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}
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static inline void arch_dup_mmap(struct mm_struct *oldmm,
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struct mm_struct *mm)
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{
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#ifdef CONFIG_64BIT
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if (oldmm->context.asce_limit < mm->context.asce_limit)
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crst_table_downgrade(mm, oldmm->context.asce_limit);
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#endif
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}
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static inline void arch_exit_mmap(struct mm_struct *mm)
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{
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}
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#endif /* __S390_MMU_CONTEXT_H */
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