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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b3ca9888f3
Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* Copyright (C) 2012-2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/reboot.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/cacheflush.h>
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#include "core.h"
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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void __iomem *sdr_ctl_base_addr;
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unsigned long socfpga_cpu1start_addr;
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extern void __init socfpga_reset_init(void);
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static void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
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if (of_property_read_u32(np, "cpu1-start-addr",
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(u32 *) &socfpga_cpu1start_addr))
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pr_err("SMP: Need cpu1-start-addr in device tree.\n");
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/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
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smp_wmb();
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sync_cache_w(&socfpga_cpu1start_addr);
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sys_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
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rst_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
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sdr_ctl_base_addr = of_iomap(np, 0);
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}
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static void __init socfpga_init_irq(void)
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{
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irqchip_init();
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socfpga_sysmgr_init();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
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socfpga_init_l2_ecc();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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socfpga_init_ocram_ecc();
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socfpga_reset_init();
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}
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static void __init socfpga_arria10_init_irq(void)
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{
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irqchip_init();
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socfpga_sysmgr_init();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
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socfpga_init_arria10_l2_ecc();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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socfpga_init_arria10_ocram_ecc();
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socfpga_reset_init();
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}
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static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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if (mode == REBOOT_HARD)
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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}
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static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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if (mode == REBOOT_HARD)
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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}
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static const char *altera_dt_match[] = {
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"altr,socfpga",
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NULL
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};
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DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = socfpga_init_irq,
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.restart = socfpga_cyclone5_restart,
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.dt_compat = altera_dt_match,
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MACHINE_END
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static const char *altera_a10_dt_match[] = {
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"altr,socfpga-arria10",
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NULL
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};
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DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = socfpga_arria10_init_irq,
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.restart = socfpga_arria10_restart,
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.dt_compat = altera_a10_dt_match,
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MACHINE_END
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