mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 06:55:20 +07:00
73c1a577b8
Reworked auto white balance feature (awb) to cope with all four channels. Implemented stretching and grey world algorithms. Using the histogram, the ISC will auto adjust the white balance during frame captures. Because each histogram needs a frame, it will take 4 frames for one adjustment. When the gains were updated by previous code, the registers for the gains were updated only on new streaming start. Now, after each full histogram the registers are updated with new gains. Also, on previous code, if the streaming stopped but not all 3 histograms finished, a new histogram was started either way. This used to lead to an error "timeout to update profile" when streaming was stopped. According to the hardware, histogram can only work together with the capture, not independently. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
287 lines
8.1 KiB
C
287 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ATMEL_ISC_REGS_H
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#define __ATMEL_ISC_REGS_H
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#include <linux/bitops.h>
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/* ISC Control Enable Register 0 */
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#define ISC_CTRLEN 0x00000000
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/* ISC Control Disable Register 0 */
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#define ISC_CTRLDIS 0x00000004
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/* ISC Control Status Register 0 */
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#define ISC_CTRLSR 0x00000008
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#define ISC_CTRL_CAPTURE BIT(0)
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#define ISC_CTRL_UPPRO BIT(1)
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#define ISC_CTRL_HISREQ BIT(2)
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#define ISC_CTRL_HISCLR BIT(3)
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/* ISC Parallel Front End Configuration 0 Register */
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#define ISC_PFE_CFG0 0x0000000c
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#define ISC_PFE_CFG0_HPOL_LOW BIT(0)
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#define ISC_PFE_CFG0_VPOL_LOW BIT(1)
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#define ISC_PFE_CFG0_PPOL_LOW BIT(2)
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#define ISC_PFE_CFG0_CCIR656 BIT(9)
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#define ISC_PFE_CFG0_CCIR_CRC BIT(10)
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#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
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#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
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#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28)
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#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28)
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#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28)
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#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
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#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
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#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)
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#define ISC_PFE_CFG0_COLEN BIT(12)
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#define ISC_PFE_CFG0_ROWEN BIT(13)
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/* ISC Parallel Front End Configuration 1 Register */
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#define ISC_PFE_CFG1 0x00000010
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#define ISC_PFE_CFG1_COLMIN(v) ((v))
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#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0)
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#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16)
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#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16)
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/* ISC Parallel Front End Configuration 2 Register */
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#define ISC_PFE_CFG2 0x00000014
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#define ISC_PFE_CFG2_ROWMIN(v) ((v))
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#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0)
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#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16)
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#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16)
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/* ISC Clock Enable Register */
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#define ISC_CLKEN 0x00000018
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/* ISC Clock Disable Register */
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#define ISC_CLKDIS 0x0000001c
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/* ISC Clock Status Register */
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#define ISC_CLKSR 0x00000020
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#define ISC_CLKSR_SIP BIT(31)
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#define ISC_CLK(n) BIT(n)
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/* ISC Clock Configuration Register */
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#define ISC_CLKCFG 0x00000024
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#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
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#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16)
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#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
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#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8))
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/* ISC Interrupt Enable Register */
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#define ISC_INTEN 0x00000028
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/* ISC Interrupt Disable Register */
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#define ISC_INTDIS 0x0000002c
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/* ISC Interrupt Mask Register */
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#define ISC_INTMASK 0x00000030
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/* ISC Interrupt Status Register */
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#define ISC_INTSR 0x00000034
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#define ISC_INT_DDONE BIT(8)
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#define ISC_INT_HISDONE BIT(12)
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/* ISC White Balance Control Register */
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#define ISC_WB_CTRL 0x00000058
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/* ISC White Balance Configuration Register */
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#define ISC_WB_CFG 0x0000005c
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/* ISC White Balance Offset for R, GR Register */
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#define ISC_WB_O_RGR 0x00000060
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/* ISC White Balance Offset for B, GB Register */
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#define ISC_WB_O_BGB 0x00000064
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/* ISC White Balance Gain for R, GR Register */
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#define ISC_WB_G_RGR 0x00000068
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/* ISC White Balance Gain for B, GB Register */
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#define ISC_WB_G_BGB 0x0000006c
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#define ISC_WB_O_ZERO_VAL (1 << 13)
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/* ISC Color Filter Array Control Register */
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#define ISC_CFA_CTRL 0x00000070
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/* ISC Color Filter Array Configuration Register */
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#define ISC_CFA_CFG 0x00000074
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#define ISC_CFA_CFG_EITPOL BIT(4)
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#define ISC_BAY_CFG_GRGR 0x0
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#define ISC_BAY_CFG_RGRG 0x1
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#define ISC_BAY_CFG_GBGB 0x2
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#define ISC_BAY_CFG_BGBG 0x3
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/* ISC Color Correction Control Register */
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#define ISC_CC_CTRL 0x00000078
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/* ISC Color Correction RR RG Register */
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#define ISC_CC_RR_RG 0x0000007c
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/* ISC Color Correction RB OR Register */
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#define ISC_CC_RB_OR 0x00000080
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/* ISC Color Correction GR GG Register */
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#define ISC_CC_GR_GG 0x00000084
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/* ISC Color Correction GB OG Register */
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#define ISC_CC_GB_OG 0x00000088
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/* ISC Color Correction BR BG Register */
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#define ISC_CC_BR_BG 0x0000008c
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/* ISC Color Correction BB OB Register */
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#define ISC_CC_BB_OB 0x00000090
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/* ISC Gamma Correction Control Register */
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#define ISC_GAM_CTRL 0x00000094
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/* ISC_Gamma Correction Blue Entry Register */
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#define ISC_GAM_BENTRY 0x00000098
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/* ISC_Gamma Correction Green Entry Register */
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#define ISC_GAM_GENTRY 0x00000198
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/* ISC_Gamma Correction Green Entry Register */
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#define ISC_GAM_RENTRY 0x00000298
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/* Color Space Conversion Control Register */
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#define ISC_CSC_CTRL 0x00000398
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/* Color Space Conversion YR YG Register */
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#define ISC_CSC_YR_YG 0x0000039c
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/* Color Space Conversion YB OY Register */
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#define ISC_CSC_YB_OY 0x000003a0
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/* Color Space Conversion CBR CBG Register */
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#define ISC_CSC_CBR_CBG 0x000003a4
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/* Color Space Conversion CBB OCB Register */
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#define ISC_CSC_CBB_OCB 0x000003a8
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/* Color Space Conversion CRR CRG Register */
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#define ISC_CSC_CRR_CRG 0x000003ac
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/* Color Space Conversion CRB OCR Register */
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#define ISC_CSC_CRB_OCR 0x000003b0
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/* Contrast And Brightness Control Register */
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#define ISC_CBC_CTRL 0x000003b4
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/* Contrast And Brightness Configuration Register */
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#define ISC_CBC_CFG 0x000003b8
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/* Brightness Register */
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#define ISC_CBC_BRIGHT 0x000003bc
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#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0)
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/* Contrast Register */
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#define ISC_CBC_CONTRAST 0x000003c0
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#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0)
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/* Subsampling 4:4:4 to 4:2:2 Control Register */
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#define ISC_SUB422_CTRL 0x000003c4
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/* Subsampling 4:2:2 to 4:2:0 Control Register */
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#define ISC_SUB420_CTRL 0x000003cc
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/* Rounding, Limiting and Packing Configuration Register */
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#define ISC_RLP_CFG 0x000003d0
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#define ISC_RLP_CFG_MODE_DAT8 0x0
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#define ISC_RLP_CFG_MODE_DAT9 0x1
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#define ISC_RLP_CFG_MODE_DAT10 0x2
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#define ISC_RLP_CFG_MODE_DAT11 0x3
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#define ISC_RLP_CFG_MODE_DAT12 0x4
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#define ISC_RLP_CFG_MODE_DATY8 0x5
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#define ISC_RLP_CFG_MODE_DATY10 0x6
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#define ISC_RLP_CFG_MODE_ARGB444 0x7
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#define ISC_RLP_CFG_MODE_ARGB555 0x8
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#define ISC_RLP_CFG_MODE_RGB565 0x9
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#define ISC_RLP_CFG_MODE_ARGB32 0xa
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#define ISC_RLP_CFG_MODE_YYCC 0xb
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#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc
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#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)
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/* Histogram Control Register */
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#define ISC_HIS_CTRL 0x000003d4
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#define ISC_HIS_CTRL_EN BIT(0)
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#define ISC_HIS_CTRL_DIS 0x0
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/* Histogram Configuration Register */
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#define ISC_HIS_CFG 0x000003d8
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#define ISC_HIS_CFG_MODE_GR 0x0
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#define ISC_HIS_CFG_MODE_R 0x1
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#define ISC_HIS_CFG_MODE_GB 0x2
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#define ISC_HIS_CFG_MODE_B 0x3
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#define ISC_HIS_CFG_MODE_Y 0x4
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#define ISC_HIS_CFG_MODE_RAW 0x5
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#define ISC_HIS_CFG_MODE_YCCIR656 0x6
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#define ISC_HIS_CFG_BAYSEL_SHIFT 4
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#define ISC_HIS_CFG_RAR BIT(8)
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/* DMA Configuration Register */
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#define ISC_DCFG 0x000003e0
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#define ISC_DCFG_IMODE_PACKED8 0x0
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#define ISC_DCFG_IMODE_PACKED16 0x1
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#define ISC_DCFG_IMODE_PACKED32 0x2
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#define ISC_DCFG_IMODE_YC422SP 0x3
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#define ISC_DCFG_IMODE_YC422P 0x4
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#define ISC_DCFG_IMODE_YC420SP 0x5
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#define ISC_DCFG_IMODE_YC420P 0x6
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#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)
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#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4)
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#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4)
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#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8)
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#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8)
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/* DMA Control Register */
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#define ISC_DCTRL 0x000003e4
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#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1)
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#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1)
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#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1)
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#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)
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#define ISC_DCTRL_IE_IS (0x0 << 4)
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/* DMA Descriptor Address Register */
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#define ISC_DNDA 0x000003e8
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/* DMA Address 0 Register */
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#define ISC_DAD0 0x000003ec
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/* DMA Address 1 Register */
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#define ISC_DAD1 0x000003f4
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/* DMA Address 2 Register */
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#define ISC_DAD2 0x000003fc
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/* Histogram Entry */
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#define ISC_HIS_ENTRY 0x00000410
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#endif
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