mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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869a53d4d7
Not needed any more since that is now done by the scheduler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1317 lines
40 KiB
C
1317 lines
40 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __AMDGPU_H__
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#define __AMDGPU_H__
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#include <linux/atomic.h>
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#include <linux/wait.h>
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#include <linux/list.h>
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#include <linux/kref.h>
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#include <linux/rbtree.h>
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#include <linux/hashtable.h>
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#include <linux/dma-fence.h>
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#include <drm/ttm/ttm_bo_api.h>
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#include <drm/ttm/ttm_bo_driver.h>
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#include <drm/ttm/ttm_placement.h>
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#include <drm/ttm/ttm_module.h>
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#include <drm/ttm/ttm_execbuf_util.h>
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#include <drm/drmP.h>
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#include <drm/drm_gem.h>
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#include <drm/amdgpu_drm.h>
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#include <drm/gpu_scheduler.h>
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#include <kgd_kfd_interface.h>
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#include "dm_pp_interface.h"
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#include "kgd_pp_interface.h"
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#include "amd_shared.h"
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#include "amdgpu_mode.h"
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#include "amdgpu_ih.h"
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#include "amdgpu_irq.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_ttm.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_gds.h"
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#include "amdgpu_sync.h"
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#include "amdgpu_ring.h"
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#include "amdgpu_vm.h"
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#include "amdgpu_dpm.h"
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#include "amdgpu_acp.h"
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#include "amdgpu_uvd.h"
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#include "amdgpu_vce.h"
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#include "amdgpu_vcn.h"
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#include "amdgpu_mn.h"
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#include "amdgpu_gmc.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_sdma.h"
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#include "amdgpu_dm.h"
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#include "amdgpu_virt.h"
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#include "amdgpu_gart.h"
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#include "amdgpu_debugfs.h"
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#include "amdgpu_job.h"
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#include "amdgpu_bo_list.h"
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#include "amdgpu_gem.h"
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/*
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* Modules parameters.
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*/
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extern int amdgpu_modeset;
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extern int amdgpu_vram_limit;
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extern int amdgpu_vis_vram_limit;
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extern int amdgpu_gart_size;
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extern int amdgpu_gtt_size;
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extern int amdgpu_moverate;
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extern int amdgpu_benchmarking;
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extern int amdgpu_testing;
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extern int amdgpu_audio;
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extern int amdgpu_disp_priority;
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extern int amdgpu_hw_i2c;
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extern int amdgpu_pcie_gen2;
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extern int amdgpu_msi;
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extern int amdgpu_lockup_timeout;
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extern int amdgpu_dpm;
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extern int amdgpu_fw_load_type;
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extern int amdgpu_aspm;
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extern int amdgpu_runtime_pm;
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extern uint amdgpu_ip_block_mask;
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extern int amdgpu_bapm;
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extern int amdgpu_deep_color;
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extern int amdgpu_vm_size;
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extern int amdgpu_vm_block_size;
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extern int amdgpu_vm_fragment_size;
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extern int amdgpu_vm_fault_stop;
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extern int amdgpu_vm_debug;
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extern int amdgpu_vm_update_mode;
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extern int amdgpu_dc;
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extern int amdgpu_sched_jobs;
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extern int amdgpu_sched_hw_submission;
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extern uint amdgpu_pcie_gen_cap;
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extern uint amdgpu_pcie_lane_cap;
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extern uint amdgpu_cg_mask;
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extern uint amdgpu_pg_mask;
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extern uint amdgpu_sdma_phase_quantum;
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extern char *amdgpu_disable_cu;
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extern char *amdgpu_virtual_display;
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extern uint amdgpu_pp_feature_mask;
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extern int amdgpu_vram_page_split;
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extern int amdgpu_ngg;
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extern int amdgpu_prim_buf_per_se;
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extern int amdgpu_pos_buf_per_se;
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extern int amdgpu_cntl_sb_buf_per_se;
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extern int amdgpu_param_buf_per_se;
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extern int amdgpu_job_hang_limit;
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extern int amdgpu_lbpw;
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extern int amdgpu_compute_multipipe;
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extern int amdgpu_gpu_recovery;
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extern int amdgpu_emu_mode;
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extern uint amdgpu_smu_memory_pool_size;
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#ifdef CONFIG_DRM_AMDGPU_SI
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extern int amdgpu_si_support;
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#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
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extern int amdgpu_cik_support;
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#endif
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#define AMDGPU_SG_THRESHOLD (256*1024*1024)
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#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
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#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
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#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
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/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
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#define AMDGPU_IB_POOL_SIZE 16
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#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
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#define AMDGPUFB_CONN_LIMIT 4
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#define AMDGPU_BIOS_NUM_SCRATCH 16
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/* hard reset data */
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#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
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/* reset flags */
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#define AMDGPU_RESET_GFX (1 << 0)
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#define AMDGPU_RESET_COMPUTE (1 << 1)
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#define AMDGPU_RESET_DMA (1 << 2)
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#define AMDGPU_RESET_CP (1 << 3)
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#define AMDGPU_RESET_GRBM (1 << 4)
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#define AMDGPU_RESET_DMA1 (1 << 5)
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#define AMDGPU_RESET_RLC (1 << 6)
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#define AMDGPU_RESET_SEM (1 << 7)
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#define AMDGPU_RESET_IH (1 << 8)
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#define AMDGPU_RESET_VMC (1 << 9)
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#define AMDGPU_RESET_MC (1 << 10)
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#define AMDGPU_RESET_DISPLAY (1 << 11)
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#define AMDGPU_RESET_UVD (1 << 12)
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#define AMDGPU_RESET_VCE (1 << 13)
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#define AMDGPU_RESET_VCE1 (1 << 14)
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/* max cursor sizes (in pixels) */
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#define CIK_CURSOR_WIDTH 128
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#define CIK_CURSOR_HEIGHT 128
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struct amdgpu_device;
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struct amdgpu_ib;
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struct amdgpu_cs_parser;
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struct amdgpu_job;
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struct amdgpu_irq_src;
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struct amdgpu_fpriv;
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struct amdgpu_bo_va_mapping;
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struct amdgpu_atif;
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enum amdgpu_cp_irq {
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AMDGPU_CP_IRQ_GFX_EOP = 0,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
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AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
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AMDGPU_CP_IRQ_LAST
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};
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enum amdgpu_thermal_irq {
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AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
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AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
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AMDGPU_THERMAL_IRQ_LAST
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};
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enum amdgpu_kiq_irq {
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AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
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AMDGPU_CP_KIQ_IRQ_LAST
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};
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int amdgpu_device_ip_set_clockgating_state(void *dev,
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enum amd_ip_block_type block_type,
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enum amd_clockgating_state state);
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int amdgpu_device_ip_set_powergating_state(void *dev,
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enum amd_ip_block_type block_type,
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enum amd_powergating_state state);
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void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
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u32 *flags);
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int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type);
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bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
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enum amd_ip_block_type block_type);
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#define AMDGPU_MAX_IP_NUM 16
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struct amdgpu_ip_block_status {
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bool valid;
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bool sw;
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bool hw;
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bool late_initialized;
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bool hang;
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};
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struct amdgpu_ip_block_version {
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const enum amd_ip_block_type type;
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const u32 major;
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const u32 minor;
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const u32 rev;
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const struct amd_ip_funcs *funcs;
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};
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struct amdgpu_ip_block {
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struct amdgpu_ip_block_status status;
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const struct amdgpu_ip_block_version *version;
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};
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int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
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enum amd_ip_block_type type,
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u32 major, u32 minor);
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struct amdgpu_ip_block *
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amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
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enum amd_ip_block_type type);
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int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
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const struct amdgpu_ip_block_version *ip_block_version);
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/*
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* BIOS.
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*/
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bool amdgpu_get_bios(struct amdgpu_device *adev);
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bool amdgpu_read_bios(struct amdgpu_device *adev);
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/*
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* Clocks
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*/
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#define AMDGPU_MAX_PPLL 3
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struct amdgpu_clock {
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struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
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struct amdgpu_pll spll;
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struct amdgpu_pll mpll;
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/* 10 Khz units */
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uint32_t default_mclk;
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uint32_t default_sclk;
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uint32_t default_dispclk;
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uint32_t current_dispclk;
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uint32_t dp_extclk;
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uint32_t max_pixel_clock;
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};
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/* sub-allocation manager, it has to be protected by another lock.
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* By conception this is an helper for other part of the driver
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* like the indirect buffer or semaphore, which both have their
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* locking.
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*
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* Principe is simple, we keep a list of sub allocation in offset
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* order (first entry has offset == 0, last entry has the highest
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* offset).
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*
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* When allocating new object we first check if there is room at
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* the end total_size - (last_object_offset + last_object_size) >=
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* alloc_size. If so we allocate new object there.
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*
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* When there is not enough room at the end, we start waiting for
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* each sub object until we reach object_offset+object_size >=
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* alloc_size, this object then become the sub object we return.
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*
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* Alignment can't be bigger than page size.
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*
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* Hole are not considered for allocation to keep things simple.
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* Assumption is that there won't be hole (all object on same
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* alignment).
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*/
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#define AMDGPU_SA_NUM_FENCE_LISTS 32
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struct amdgpu_sa_manager {
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wait_queue_head_t wq;
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struct amdgpu_bo *bo;
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struct list_head *hole;
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struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
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struct list_head olist;
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unsigned size;
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uint64_t gpu_addr;
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void *cpu_ptr;
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uint32_t domain;
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uint32_t align;
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};
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/* sub-allocation buffer */
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struct amdgpu_sa_bo {
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struct list_head olist;
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struct list_head flist;
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struct amdgpu_sa_manager *manager;
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unsigned soffset;
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unsigned eoffset;
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struct dma_fence *fence;
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};
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int amdgpu_fence_slab_init(void);
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void amdgpu_fence_slab_fini(void);
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/*
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* GPU doorbell structures, functions & helpers
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*/
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typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
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{
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AMDGPU_DOORBELL_KIQ = 0x000,
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AMDGPU_DOORBELL_HIQ = 0x001,
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AMDGPU_DOORBELL_DIQ = 0x002,
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AMDGPU_DOORBELL_MEC_RING0 = 0x010,
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AMDGPU_DOORBELL_MEC_RING1 = 0x011,
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AMDGPU_DOORBELL_MEC_RING2 = 0x012,
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AMDGPU_DOORBELL_MEC_RING3 = 0x013,
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AMDGPU_DOORBELL_MEC_RING4 = 0x014,
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AMDGPU_DOORBELL_MEC_RING5 = 0x015,
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AMDGPU_DOORBELL_MEC_RING6 = 0x016,
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AMDGPU_DOORBELL_MEC_RING7 = 0x017,
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AMDGPU_DOORBELL_GFX_RING0 = 0x020,
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AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
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AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
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AMDGPU_DOORBELL_IH = 0x1E8,
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AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
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AMDGPU_DOORBELL_INVALID = 0xFFFF
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} AMDGPU_DOORBELL_ASSIGNMENT;
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struct amdgpu_doorbell {
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/* doorbell mmio */
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resource_size_t base;
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resource_size_t size;
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u32 __iomem *ptr;
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u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
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};
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/*
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* 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
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*/
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typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
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{
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/*
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* All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
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* a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
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* Compute related doorbells are allocated from 0x00 to 0x8a
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*/
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/* kernel scheduling */
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AMDGPU_DOORBELL64_KIQ = 0x00,
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/* HSA interface queue and debug queue */
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AMDGPU_DOORBELL64_HIQ = 0x01,
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AMDGPU_DOORBELL64_DIQ = 0x02,
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/* Compute engines */
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AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
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AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
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AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
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AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
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AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
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AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
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AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
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AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
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/* User queue doorbell range (128 doorbells) */
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AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
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AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
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/* Graphics engine */
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AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
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/*
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* Other graphics doorbells can be allocated here: from 0x8c to 0xef
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* Graphics voltage island aperture 1
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* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
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*/
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/* sDMA engines */
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AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
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AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
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AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
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/* Interrupt handler */
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AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
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AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
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AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
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/* VCN engine use 32 bits doorbell */
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AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
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AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
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AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
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AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
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/* overlap the doorbell assignment with VCN as they are mutually exclusive
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* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
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*/
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AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
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AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
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AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
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AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
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|
AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
|
|
AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
|
|
AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
|
|
AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
|
|
|
|
AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
|
|
AMDGPU_DOORBELL64_INVALID = 0xFFFF
|
|
} AMDGPU_DOORBELL64_ASSIGNMENT;
|
|
|
|
/*
|
|
* IRQS.
|
|
*/
|
|
|
|
struct amdgpu_flip_work {
|
|
struct delayed_work flip_work;
|
|
struct work_struct unpin_work;
|
|
struct amdgpu_device *adev;
|
|
int crtc_id;
|
|
u32 target_vblank;
|
|
uint64_t base;
|
|
struct drm_pending_vblank_event *event;
|
|
struct amdgpu_bo *old_abo;
|
|
struct dma_fence *excl;
|
|
unsigned shared_count;
|
|
struct dma_fence **shared;
|
|
struct dma_fence_cb cb;
|
|
bool async;
|
|
};
|
|
|
|
|
|
/*
|
|
* CP & rings.
|
|
*/
|
|
|
|
struct amdgpu_ib {
|
|
struct amdgpu_sa_bo *sa_bo;
|
|
uint32_t length_dw;
|
|
uint64_t gpu_addr;
|
|
uint32_t *ptr;
|
|
uint32_t flags;
|
|
};
|
|
|
|
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
|
|
|
|
/*
|
|
* context related structures
|
|
*/
|
|
|
|
struct amdgpu_ctx_ring {
|
|
uint64_t sequence;
|
|
struct dma_fence **fences;
|
|
struct drm_sched_entity entity;
|
|
};
|
|
|
|
struct amdgpu_ctx {
|
|
struct kref refcount;
|
|
struct amdgpu_device *adev;
|
|
unsigned reset_counter;
|
|
unsigned reset_counter_query;
|
|
uint32_t vram_lost_counter;
|
|
spinlock_t ring_lock;
|
|
struct dma_fence **fences;
|
|
struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
|
|
bool preamble_presented;
|
|
enum drm_sched_priority init_priority;
|
|
enum drm_sched_priority override_priority;
|
|
struct mutex lock;
|
|
atomic_t guilty;
|
|
};
|
|
|
|
struct amdgpu_ctx_mgr {
|
|
struct amdgpu_device *adev;
|
|
struct mutex lock;
|
|
/* protected by lock */
|
|
struct idr ctx_handles;
|
|
};
|
|
|
|
struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
|
|
int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
|
|
|
|
int amdgpu_ctx_get_ring(struct amdgpu_ctx *ctx,
|
|
u32 hw_ip, u32 instance, u32 ring,
|
|
struct amdgpu_ring **out_ring);
|
|
int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
|
|
struct dma_fence *fence, uint64_t *seq);
|
|
struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
|
|
struct amdgpu_ring *ring, uint64_t seq);
|
|
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
|
|
enum drm_sched_priority priority);
|
|
|
|
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
|
|
|
|
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
|
|
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
|
|
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
|
|
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
|
|
|
|
|
|
/*
|
|
* file private structure
|
|
*/
|
|
|
|
struct amdgpu_fpriv {
|
|
struct amdgpu_vm vm;
|
|
struct amdgpu_bo_va *prt_va;
|
|
struct amdgpu_bo_va *csa_va;
|
|
struct mutex bo_list_lock;
|
|
struct idr bo_list_handles;
|
|
struct amdgpu_ctx_mgr ctx_mgr;
|
|
};
|
|
|
|
int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
|
|
unsigned size, struct amdgpu_ib *ib);
|
|
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
|
|
struct dma_fence *f);
|
|
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
|
|
struct amdgpu_ib *ibs, struct amdgpu_job *job,
|
|
struct dma_fence **f);
|
|
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
|
|
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
|
|
int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
|
|
|
|
/*
|
|
* CS.
|
|
*/
|
|
struct amdgpu_cs_chunk {
|
|
uint32_t chunk_id;
|
|
uint32_t length_dw;
|
|
void *kdata;
|
|
};
|
|
|
|
struct amdgpu_cs_parser {
|
|
struct amdgpu_device *adev;
|
|
struct drm_file *filp;
|
|
struct amdgpu_ctx *ctx;
|
|
|
|
/* chunks */
|
|
unsigned nchunks;
|
|
struct amdgpu_cs_chunk *chunks;
|
|
|
|
/* scheduler job object */
|
|
struct amdgpu_job *job;
|
|
struct amdgpu_ring *ring;
|
|
|
|
/* buffer objects */
|
|
struct ww_acquire_ctx ticket;
|
|
struct amdgpu_bo_list *bo_list;
|
|
struct amdgpu_mn *mn;
|
|
struct amdgpu_bo_list_entry vm_pd;
|
|
struct list_head validated;
|
|
struct dma_fence *fence;
|
|
uint64_t bytes_moved_threshold;
|
|
uint64_t bytes_moved_vis_threshold;
|
|
uint64_t bytes_moved;
|
|
uint64_t bytes_moved_vis;
|
|
struct amdgpu_bo_list_entry *evictable;
|
|
|
|
/* user fence */
|
|
struct amdgpu_bo_list_entry uf_entry;
|
|
|
|
unsigned num_post_dep_syncobjs;
|
|
struct drm_syncobj **post_dep_syncobjs;
|
|
};
|
|
|
|
static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
|
|
uint32_t ib_idx, int idx)
|
|
{
|
|
return p->job->ibs[ib_idx].ptr[idx];
|
|
}
|
|
|
|
static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
|
|
uint32_t ib_idx, int idx,
|
|
uint32_t value)
|
|
{
|
|
p->job->ibs[ib_idx].ptr[idx] = value;
|
|
}
|
|
|
|
/*
|
|
* Writeback
|
|
*/
|
|
#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
|
|
|
|
struct amdgpu_wb {
|
|
struct amdgpu_bo *wb_obj;
|
|
volatile uint32_t *wb;
|
|
uint64_t gpu_addr;
|
|
u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
|
|
unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
|
|
};
|
|
|
|
int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
|
|
void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
|
|
|
|
/*
|
|
* Benchmarking
|
|
*/
|
|
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
|
|
|
|
|
|
/*
|
|
* Testing
|
|
*/
|
|
void amdgpu_test_moves(struct amdgpu_device *adev);
|
|
|
|
|
|
/*
|
|
* amdgpu smumgr functions
|
|
*/
|
|
struct amdgpu_smumgr_funcs {
|
|
int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
|
|
int (*request_smu_load_fw)(struct amdgpu_device *adev);
|
|
int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
|
|
};
|
|
|
|
/*
|
|
* amdgpu smumgr
|
|
*/
|
|
struct amdgpu_smumgr {
|
|
struct amdgpu_bo *toc_buf;
|
|
struct amdgpu_bo *smu_buf;
|
|
/* asic priv smu data */
|
|
void *priv;
|
|
spinlock_t smu_lock;
|
|
/* smumgr functions */
|
|
const struct amdgpu_smumgr_funcs *smumgr_funcs;
|
|
/* ucode loading complete flag */
|
|
uint32_t fw_flags;
|
|
};
|
|
|
|
/*
|
|
* ASIC specific register table accessible by UMD
|
|
*/
|
|
struct amdgpu_allowed_register_entry {
|
|
uint32_t reg_offset;
|
|
bool grbm_indexed;
|
|
};
|
|
|
|
/*
|
|
* ASIC specific functions.
|
|
*/
|
|
struct amdgpu_asic_funcs {
|
|
bool (*read_disabled_bios)(struct amdgpu_device *adev);
|
|
bool (*read_bios_from_rom)(struct amdgpu_device *adev,
|
|
u8 *bios, u32 length_bytes);
|
|
int (*read_register)(struct amdgpu_device *adev, u32 se_num,
|
|
u32 sh_num, u32 reg_offset, u32 *value);
|
|
void (*set_vga_state)(struct amdgpu_device *adev, bool state);
|
|
int (*reset)(struct amdgpu_device *adev);
|
|
/* get the reference clock */
|
|
u32 (*get_xclk)(struct amdgpu_device *adev);
|
|
/* MM block clocks */
|
|
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
|
|
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
|
|
/* static power management */
|
|
int (*get_pcie_lanes)(struct amdgpu_device *adev);
|
|
void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
|
|
/* get config memsize register */
|
|
u32 (*get_config_memsize)(struct amdgpu_device *adev);
|
|
/* flush hdp write queue */
|
|
void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
|
|
/* invalidate hdp read cache */
|
|
void (*invalidate_hdp)(struct amdgpu_device *adev,
|
|
struct amdgpu_ring *ring);
|
|
/* check if the asic needs a full reset of if soft reset will work */
|
|
bool (*need_full_reset)(struct amdgpu_device *adev);
|
|
};
|
|
|
|
/*
|
|
* IOCTL.
|
|
*/
|
|
int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
|
|
int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
|
|
int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
|
|
int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp);
|
|
|
|
/* VRAM scratch page for HDP bug, default vram page */
|
|
struct amdgpu_vram_scratch {
|
|
struct amdgpu_bo *robj;
|
|
volatile uint32_t *ptr;
|
|
u64 gpu_addr;
|
|
};
|
|
|
|
/*
|
|
* ACPI
|
|
*/
|
|
struct amdgpu_atcs_functions {
|
|
bool get_ext_state;
|
|
bool pcie_perf_req;
|
|
bool pcie_dev_rdy;
|
|
bool pcie_bus_width;
|
|
};
|
|
|
|
struct amdgpu_atcs {
|
|
struct amdgpu_atcs_functions functions;
|
|
};
|
|
|
|
/*
|
|
* Firmware VRAM reservation
|
|
*/
|
|
struct amdgpu_fw_vram_usage {
|
|
u64 start_offset;
|
|
u64 size;
|
|
struct amdgpu_bo *reserved_bo;
|
|
void *va;
|
|
};
|
|
|
|
/*
|
|
* CGS
|
|
*/
|
|
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
|
|
void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
|
|
|
|
/*
|
|
* Core structure, functions and helpers.
|
|
*/
|
|
typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
|
|
typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
|
|
|
|
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
|
|
typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
|
|
|
|
|
|
/*
|
|
* amdgpu nbio functions
|
|
*
|
|
*/
|
|
struct nbio_hdp_flush_reg {
|
|
u32 ref_and_mask_cp0;
|
|
u32 ref_and_mask_cp1;
|
|
u32 ref_and_mask_cp2;
|
|
u32 ref_and_mask_cp3;
|
|
u32 ref_and_mask_cp4;
|
|
u32 ref_and_mask_cp5;
|
|
u32 ref_and_mask_cp6;
|
|
u32 ref_and_mask_cp7;
|
|
u32 ref_and_mask_cp8;
|
|
u32 ref_and_mask_cp9;
|
|
u32 ref_and_mask_sdma0;
|
|
u32 ref_and_mask_sdma1;
|
|
};
|
|
|
|
struct amdgpu_nbio_funcs {
|
|
const struct nbio_hdp_flush_reg *hdp_flush_reg;
|
|
u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
|
|
u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
|
|
u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
|
|
u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
|
|
u32 (*get_rev_id)(struct amdgpu_device *adev);
|
|
void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
|
|
void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
|
|
u32 (*get_memsize)(struct amdgpu_device *adev);
|
|
void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
|
|
bool use_doorbell, int doorbell_index);
|
|
void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
void (*ih_doorbell_range)(struct amdgpu_device *adev,
|
|
bool use_doorbell, int doorbell_index);
|
|
void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
void (*get_clockgating_state)(struct amdgpu_device *adev,
|
|
u32 *flags);
|
|
void (*ih_control)(struct amdgpu_device *adev);
|
|
void (*init_registers)(struct amdgpu_device *adev);
|
|
void (*detect_hw_virt)(struct amdgpu_device *adev);
|
|
};
|
|
|
|
struct amdgpu_df_funcs {
|
|
void (*init)(struct amdgpu_device *adev);
|
|
void (*enable_broadcast_mode)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
|
|
u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
|
|
void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
void (*get_clockgating_state)(struct amdgpu_device *adev,
|
|
u32 *flags);
|
|
void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
|
|
bool enable);
|
|
};
|
|
/* Define the HW IP blocks will be used in driver , add more if necessary */
|
|
enum amd_hw_ip_block_type {
|
|
GC_HWIP = 1,
|
|
HDP_HWIP,
|
|
SDMA0_HWIP,
|
|
SDMA1_HWIP,
|
|
MMHUB_HWIP,
|
|
ATHUB_HWIP,
|
|
NBIO_HWIP,
|
|
MP0_HWIP,
|
|
MP1_HWIP,
|
|
UVD_HWIP,
|
|
VCN_HWIP = UVD_HWIP,
|
|
VCE_HWIP,
|
|
DF_HWIP,
|
|
DCE_HWIP,
|
|
OSSSYS_HWIP,
|
|
SMUIO_HWIP,
|
|
PWR_HWIP,
|
|
NBIF_HWIP,
|
|
THM_HWIP,
|
|
CLK_HWIP,
|
|
MAX_HWIP
|
|
};
|
|
|
|
#define HWIP_MAX_INSTANCE 6
|
|
|
|
struct amd_powerplay {
|
|
void *pp_handle;
|
|
const struct amd_pm_funcs *pp_funcs;
|
|
uint32_t pp_feature;
|
|
};
|
|
|
|
#define AMDGPU_RESET_MAGIC_NUM 64
|
|
struct amdgpu_device {
|
|
struct device *dev;
|
|
struct drm_device *ddev;
|
|
struct pci_dev *pdev;
|
|
|
|
#ifdef CONFIG_DRM_AMD_ACP
|
|
struct amdgpu_acp acp;
|
|
#endif
|
|
|
|
/* ASIC */
|
|
enum amd_asic_type asic_type;
|
|
uint32_t family;
|
|
uint32_t rev_id;
|
|
uint32_t external_rev_id;
|
|
unsigned long flags;
|
|
int usec_timeout;
|
|
const struct amdgpu_asic_funcs *asic_funcs;
|
|
bool shutdown;
|
|
bool need_dma32;
|
|
bool need_swiotlb;
|
|
bool accel_working;
|
|
struct work_struct reset_work;
|
|
struct notifier_block acpi_nb;
|
|
struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
|
|
struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
|
|
unsigned debugfs_count;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
|
|
#endif
|
|
struct amdgpu_atif *atif;
|
|
struct amdgpu_atcs atcs;
|
|
struct mutex srbm_mutex;
|
|
/* GRBM index mutex. Protects concurrent access to GRBM index */
|
|
struct mutex grbm_idx_mutex;
|
|
struct dev_pm_domain vga_pm_domain;
|
|
bool have_disp_power_ref;
|
|
|
|
/* BIOS */
|
|
bool is_atom_fw;
|
|
uint8_t *bios;
|
|
uint32_t bios_size;
|
|
struct amdgpu_bo *stolen_vga_memory;
|
|
uint32_t bios_scratch_reg_offset;
|
|
uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
|
|
|
|
/* Register/doorbell mmio */
|
|
resource_size_t rmmio_base;
|
|
resource_size_t rmmio_size;
|
|
void __iomem *rmmio;
|
|
/* protects concurrent MM_INDEX/DATA based register access */
|
|
spinlock_t mmio_idx_lock;
|
|
/* protects concurrent SMC based register access */
|
|
spinlock_t smc_idx_lock;
|
|
amdgpu_rreg_t smc_rreg;
|
|
amdgpu_wreg_t smc_wreg;
|
|
/* protects concurrent PCIE register access */
|
|
spinlock_t pcie_idx_lock;
|
|
amdgpu_rreg_t pcie_rreg;
|
|
amdgpu_wreg_t pcie_wreg;
|
|
amdgpu_rreg_t pciep_rreg;
|
|
amdgpu_wreg_t pciep_wreg;
|
|
/* protects concurrent UVD register access */
|
|
spinlock_t uvd_ctx_idx_lock;
|
|
amdgpu_rreg_t uvd_ctx_rreg;
|
|
amdgpu_wreg_t uvd_ctx_wreg;
|
|
/* protects concurrent DIDT register access */
|
|
spinlock_t didt_idx_lock;
|
|
amdgpu_rreg_t didt_rreg;
|
|
amdgpu_wreg_t didt_wreg;
|
|
/* protects concurrent gc_cac register access */
|
|
spinlock_t gc_cac_idx_lock;
|
|
amdgpu_rreg_t gc_cac_rreg;
|
|
amdgpu_wreg_t gc_cac_wreg;
|
|
/* protects concurrent se_cac register access */
|
|
spinlock_t se_cac_idx_lock;
|
|
amdgpu_rreg_t se_cac_rreg;
|
|
amdgpu_wreg_t se_cac_wreg;
|
|
/* protects concurrent ENDPOINT (audio) register access */
|
|
spinlock_t audio_endpt_idx_lock;
|
|
amdgpu_block_rreg_t audio_endpt_rreg;
|
|
amdgpu_block_wreg_t audio_endpt_wreg;
|
|
void __iomem *rio_mem;
|
|
resource_size_t rio_mem_size;
|
|
struct amdgpu_doorbell doorbell;
|
|
|
|
/* clock/pll info */
|
|
struct amdgpu_clock clock;
|
|
|
|
/* MC */
|
|
struct amdgpu_gmc gmc;
|
|
struct amdgpu_gart gart;
|
|
dma_addr_t dummy_page_addr;
|
|
struct amdgpu_vm_manager vm_manager;
|
|
struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
|
|
|
|
/* memory management */
|
|
struct amdgpu_mman mman;
|
|
struct amdgpu_vram_scratch vram_scratch;
|
|
struct amdgpu_wb wb;
|
|
atomic64_t num_bytes_moved;
|
|
atomic64_t num_evictions;
|
|
atomic64_t num_vram_cpu_page_faults;
|
|
atomic_t gpu_reset_counter;
|
|
atomic_t vram_lost_counter;
|
|
|
|
/* data for buffer migration throttling */
|
|
struct {
|
|
spinlock_t lock;
|
|
s64 last_update_us;
|
|
s64 accum_us; /* accumulated microseconds */
|
|
s64 accum_us_vis; /* for visible VRAM */
|
|
u32 log2_max_MBps;
|
|
} mm_stats;
|
|
|
|
/* display */
|
|
bool enable_virtual_display;
|
|
struct amdgpu_mode_info mode_info;
|
|
/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
|
|
struct work_struct hotplug_work;
|
|
struct amdgpu_irq_src crtc_irq;
|
|
struct amdgpu_irq_src pageflip_irq;
|
|
struct amdgpu_irq_src hpd_irq;
|
|
|
|
/* rings */
|
|
u64 fence_context;
|
|
unsigned num_rings;
|
|
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
|
|
bool ib_pool_ready;
|
|
struct amdgpu_sa_manager ring_tmp_bo;
|
|
|
|
/* interrupts */
|
|
struct amdgpu_irq irq;
|
|
|
|
/* powerplay */
|
|
struct amd_powerplay powerplay;
|
|
bool pp_force_state_enabled;
|
|
|
|
/* dpm */
|
|
struct amdgpu_pm pm;
|
|
u32 cg_flags;
|
|
u32 pg_flags;
|
|
|
|
/* amdgpu smumgr */
|
|
struct amdgpu_smumgr smu;
|
|
|
|
/* gfx */
|
|
struct amdgpu_gfx gfx;
|
|
|
|
/* sdma */
|
|
struct amdgpu_sdma sdma;
|
|
|
|
/* uvd */
|
|
struct amdgpu_uvd uvd;
|
|
|
|
/* vce */
|
|
struct amdgpu_vce vce;
|
|
|
|
/* vcn */
|
|
struct amdgpu_vcn vcn;
|
|
|
|
/* firmwares */
|
|
struct amdgpu_firmware firmware;
|
|
|
|
/* PSP */
|
|
struct psp_context psp;
|
|
|
|
/* GDS */
|
|
struct amdgpu_gds gds;
|
|
|
|
/* display related functionality */
|
|
struct amdgpu_display_manager dm;
|
|
|
|
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
|
|
int num_ip_blocks;
|
|
struct mutex mn_lock;
|
|
DECLARE_HASHTABLE(mn_hash, 7);
|
|
|
|
/* tracking pinned memory */
|
|
atomic64_t vram_pin_size;
|
|
atomic64_t visible_pin_size;
|
|
atomic64_t gart_pin_size;
|
|
|
|
/* amdkfd interface */
|
|
struct kfd_dev *kfd;
|
|
|
|
/* soc15 register offset based on ip, instance and segment */
|
|
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
|
|
|
const struct amdgpu_nbio_funcs *nbio_funcs;
|
|
const struct amdgpu_df_funcs *df_funcs;
|
|
|
|
/* delayed work_func for deferring clockgating during resume */
|
|
struct delayed_work late_init_work;
|
|
|
|
struct amdgpu_virt virt;
|
|
/* firmware VRAM reservation */
|
|
struct amdgpu_fw_vram_usage fw_vram_usage;
|
|
|
|
/* link all shadow bo */
|
|
struct list_head shadow_list;
|
|
struct mutex shadow_list_lock;
|
|
/* keep an lru list of rings by HW IP */
|
|
struct list_head ring_lru_list;
|
|
spinlock_t ring_lru_list_lock;
|
|
|
|
/* record hw reset is performed */
|
|
bool has_hw_reset;
|
|
u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
|
|
|
|
/* record last mm index being written through WREG32*/
|
|
unsigned long last_mm_index;
|
|
bool in_gpu_reset;
|
|
struct mutex lock_reset;
|
|
};
|
|
|
|
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
|
|
{
|
|
return container_of(bdev, struct amdgpu_device, mman.bdev);
|
|
}
|
|
|
|
int amdgpu_device_init(struct amdgpu_device *adev,
|
|
struct drm_device *ddev,
|
|
struct pci_dev *pdev,
|
|
uint32_t flags);
|
|
void amdgpu_device_fini(struct amdgpu_device *adev);
|
|
int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
|
|
|
|
uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
|
|
uint32_t acc_flags);
|
|
void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
|
|
uint32_t acc_flags);
|
|
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
|
|
uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
|
|
|
|
u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
|
|
void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
|
|
|
|
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
|
|
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
|
|
u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
|
|
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
|
|
|
|
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
|
|
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
|
|
|
|
int emu_soc_asic_init(struct amdgpu_device *adev);
|
|
|
|
/*
|
|
* Registers read & write functions.
|
|
*/
|
|
|
|
#define AMDGPU_REGS_IDX (1<<0)
|
|
#define AMDGPU_REGS_NO_KIQ (1<<1)
|
|
|
|
#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
|
|
#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
|
|
|
|
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
|
|
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
|
|
|
|
#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
|
|
#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
|
|
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
|
|
#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
|
|
#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
|
|
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
|
|
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
|
|
#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
|
|
#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
|
|
#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
|
|
#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
|
|
#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
|
|
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
|
|
#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
|
|
#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
|
|
#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
|
|
#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
|
|
#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
|
|
#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
|
|
#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
|
|
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
|
|
#define WREG32_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32(reg, tmp_); \
|
|
} while (0)
|
|
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
|
|
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
|
|
#define WREG32_PLL_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32_PLL(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32_PLL(reg, tmp_); \
|
|
} while (0)
|
|
#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
|
|
#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
|
|
#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
|
|
|
|
#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
|
|
#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
|
|
#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
|
|
#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
|
|
|
|
#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
|
|
#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
|
|
|
|
#define REG_SET_FIELD(orig_val, reg, field, field_val) \
|
|
(((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
|
|
(REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
|
|
|
|
#define REG_GET_FIELD(value, reg, field) \
|
|
(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
|
|
|
|
#define WREG32_FIELD(reg, field, val) \
|
|
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
|
|
|
#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
|
|
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
|
|
|
|
/*
|
|
* BIOS helpers.
|
|
*/
|
|
#define RBIOS8(i) (adev->bios[i])
|
|
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
|
|
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
|
|
|
|
/*
|
|
* ASICs macro.
|
|
*/
|
|
#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
|
|
#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
|
|
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
|
|
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
|
|
#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
|
|
#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
|
|
#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
|
|
#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
|
|
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
|
|
#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
|
|
#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
|
|
#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
|
|
#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
|
|
#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
|
|
#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
|
|
|
|
/* Common functions */
|
|
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
|
|
struct amdgpu_job* job, bool force);
|
|
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
|
|
bool amdgpu_device_need_post(struct amdgpu_device *adev);
|
|
|
|
void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
|
|
u64 num_vis_bytes);
|
|
void amdgpu_device_vram_location(struct amdgpu_device *adev,
|
|
struct amdgpu_gmc *mc, u64 base);
|
|
void amdgpu_device_gart_location(struct amdgpu_device *adev,
|
|
struct amdgpu_gmc *mc);
|
|
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
|
|
void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
|
|
const u32 *registers,
|
|
const u32 array_size);
|
|
|
|
bool amdgpu_device_is_px(struct drm_device *dev);
|
|
/* atpx handler */
|
|
#if defined(CONFIG_VGA_SWITCHEROO)
|
|
void amdgpu_register_atpx_handler(void);
|
|
void amdgpu_unregister_atpx_handler(void);
|
|
bool amdgpu_has_atpx_dgpu_power_cntl(void);
|
|
bool amdgpu_is_atpx_hybrid(void);
|
|
bool amdgpu_atpx_dgpu_req_power_for_displays(void);
|
|
bool amdgpu_has_atpx(void);
|
|
#else
|
|
static inline void amdgpu_register_atpx_handler(void) {}
|
|
static inline void amdgpu_unregister_atpx_handler(void) {}
|
|
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
|
|
static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
|
|
static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
|
|
static inline bool amdgpu_has_atpx(void) { return false; }
|
|
#endif
|
|
|
|
#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
|
|
void *amdgpu_atpx_get_dhandle(void);
|
|
#else
|
|
static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
|
|
#endif
|
|
|
|
/*
|
|
* KMS
|
|
*/
|
|
extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
|
|
extern const int amdgpu_max_kms_ioctl;
|
|
|
|
int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
|
|
void amdgpu_driver_unload_kms(struct drm_device *dev);
|
|
void amdgpu_driver_lastclose_kms(struct drm_device *dev);
|
|
int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
|
|
void amdgpu_driver_postclose_kms(struct drm_device *dev,
|
|
struct drm_file *file_priv);
|
|
int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
|
|
int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
|
|
int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
|
|
u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
|
|
int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
|
|
void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
|
|
long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg);
|
|
|
|
/*
|
|
* functions used by amdgpu_encoder.c
|
|
*/
|
|
struct amdgpu_afmt_acr {
|
|
u32 clock;
|
|
|
|
int n_32khz;
|
|
int cts_32khz;
|
|
|
|
int n_44_1khz;
|
|
int cts_44_1khz;
|
|
|
|
int n_48khz;
|
|
int cts_48khz;
|
|
|
|
};
|
|
|
|
struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
|
|
|
|
/* amdgpu_acpi.c */
|
|
#if defined(CONFIG_ACPI)
|
|
int amdgpu_acpi_init(struct amdgpu_device *adev);
|
|
void amdgpu_acpi_fini(struct amdgpu_device *adev);
|
|
bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
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int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
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u8 perf_req, bool advertise);
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int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
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#else
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static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
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static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
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#endif
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int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
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uint64_t addr, struct amdgpu_bo **bo,
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struct amdgpu_bo_va_mapping **mapping);
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#if defined(CONFIG_DRM_AMD_DC)
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int amdgpu_dm_display_resume(struct amdgpu_device *adev );
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#else
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static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
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#endif
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#include "amdgpu_object.h"
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#endif
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