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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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096b3224d5
Currently, if cpuidle is disabled or not supported, powertop reports zero wakeups and zero events. This is due to the cpu_idle tracepoints are missing. This patch is to make cpu_idle tracepoints always available even if cpuidle is disabled or not supported. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
376 lines
9.0 KiB
C
376 lines
9.0 KiB
C
/*
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* Based on arch/arm/kernel/process.c
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*
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* Original Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 1996-2000 Russell King - Converted to ARM.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h>
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#include <linux/compat.h>
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#include <linux/efi.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <linux/interrupt.h>
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#include <linux/kallsyms.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/elfcore.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/utsname.h>
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#include <linux/uaccess.h>
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#include <linux/random.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/personality.h>
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#include <linux/notifier.h>
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#include <trace/events/power.h>
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#include <asm/compat.h>
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#include <asm/cacheflush.h>
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#include <asm/fpsimd.h>
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#include <asm/mmu_context.h>
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#include <asm/processor.h>
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#include <asm/stacktrace.h>
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#ifdef CONFIG_CC_STACKPROTECTOR
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#include <linux/stackprotector.h>
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unsigned long __stack_chk_guard __read_mostly;
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EXPORT_SYMBOL(__stack_chk_guard);
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#endif
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/*
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* Function pointers to optional machine specific functions
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*/
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void (*pm_power_off)(void);
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EXPORT_SYMBOL_GPL(pm_power_off);
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void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
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/*
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* This is our default idle handler.
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*/
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void arch_cpu_idle(void)
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{
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/*
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* This should do all the clock switching and wait for interrupt
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* tricks
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*/
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trace_cpu_idle_rcuidle(1, smp_processor_id());
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cpu_do_idle();
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local_irq_enable();
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void arch_cpu_idle_dead(void)
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{
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cpu_die();
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}
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#endif
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/*
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* Called by kexec, immediately prior to machine_kexec().
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*
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* This must completely disable all secondary CPUs; simply causing those CPUs
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* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
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* kexec'd kernel to use any and all RAM as it sees fit, without having to
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* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
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* functionality embodied in disable_nonboot_cpus() to achieve this.
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*/
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void machine_shutdown(void)
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{
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disable_nonboot_cpus();
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}
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/*
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* Halting simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this.
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*/
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void machine_halt(void)
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{
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local_irq_disable();
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smp_send_stop();
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while (1);
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}
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/*
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* Power-off simply requires that the secondary CPUs stop performing any
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* activity (executing tasks, handling interrupts). smp_send_stop()
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* achieves this. When the system power is turned off, it will take all CPUs
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* with it.
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*/
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void machine_power_off(void)
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{
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local_irq_disable();
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smp_send_stop();
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if (pm_power_off)
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pm_power_off();
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}
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/*
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* Restart requires that the secondary CPUs stop performing any activity
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* while the primary CPU resets the system. Systems with multiple CPUs must
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* provide a HW restart implementation, to ensure that all CPUs reset at once.
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* This is required so that any code running after reset on the primary CPU
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* doesn't have to co-ordinate with other CPUs to ensure they aren't still
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* executing pre-reset code, and using RAM that the primary CPU's code wishes
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* to use. Implementing such co-ordination would be essentially impossible.
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*/
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void machine_restart(char *cmd)
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{
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/* Disable interrupts first */
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local_irq_disable();
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smp_send_stop();
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/*
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* UpdateCapsule() depends on the system being reset via
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* ResetSystem().
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*/
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if (efi_enabled(EFI_RUNTIME_SERVICES))
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efi_reboot(reboot_mode, NULL);
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/* Now call the architecture specific reboot code. */
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if (arm_pm_restart)
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arm_pm_restart(reboot_mode, cmd);
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else
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do_kernel_restart(cmd);
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/*
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* Whoops - the architecture was unable to reboot.
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*/
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printk("Reboot failed -- System halted\n");
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while (1);
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}
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void __show_regs(struct pt_regs *regs)
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{
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int i, top_reg;
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u64 lr, sp;
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if (compat_user_mode(regs)) {
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lr = regs->compat_lr;
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sp = regs->compat_sp;
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top_reg = 12;
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} else {
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lr = regs->regs[30];
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sp = regs->sp;
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top_reg = 29;
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}
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show_regs_print_info(KERN_DEFAULT);
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print_symbol("PC is at %s\n", instruction_pointer(regs));
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print_symbol("LR is at %s\n", lr);
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printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
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regs->pc, lr, regs->pstate);
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printk("sp : %016llx\n", sp);
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for (i = top_reg; i >= 0; i--) {
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printk("x%-2d: %016llx ", i, regs->regs[i]);
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if (i % 2 == 0)
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printk("\n");
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}
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printk("\n");
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}
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void show_regs(struct pt_regs * regs)
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{
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printk("\n");
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__show_regs(regs);
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}
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/*
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* Free current thread data structures etc..
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*/
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void exit_thread(void)
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{
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}
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static void tls_thread_flush(void)
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{
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asm ("msr tpidr_el0, xzr");
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if (is_compat_task()) {
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current->thread.tp_value = 0;
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/*
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* We need to ensure ordering between the shadow state and the
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* hardware state, so that we don't corrupt the hardware state
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* with a stale shadow state during context switch.
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*/
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barrier();
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asm ("msr tpidrro_el0, xzr");
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}
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}
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void flush_thread(void)
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{
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fpsimd_flush_thread();
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tls_thread_flush();
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flush_ptrace_hw_breakpoint(current);
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}
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void release_thread(struct task_struct *dead_task)
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{
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}
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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if (current->mm)
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fpsimd_preserve_current_state();
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*dst = *src;
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return 0;
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}
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asmlinkage void ret_from_fork(void) asm("ret_from_fork");
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int copy_thread(unsigned long clone_flags, unsigned long stack_start,
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unsigned long stk_sz, struct task_struct *p)
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{
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struct pt_regs *childregs = task_pt_regs(p);
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memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
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if (likely(!(p->flags & PF_KTHREAD))) {
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*childregs = *current_pt_regs();
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childregs->regs[0] = 0;
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/*
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* Read the current TLS pointer from tpidr_el0 as it may be
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* out-of-sync with the saved value.
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*/
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asm("mrs %0, tpidr_el0" : "=r" (*task_user_tls(p)));
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if (stack_start) {
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if (is_compat_thread(task_thread_info(p)))
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childregs->compat_sp = stack_start;
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/* 16-byte aligned stack mandatory on AArch64 */
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else if (stack_start & 15)
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return -EINVAL;
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else
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childregs->sp = stack_start;
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}
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/*
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* If a TLS pointer was passed to clone (4th argument), use it
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* for the new thread.
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*/
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if (clone_flags & CLONE_SETTLS)
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p->thread.tp_value = childregs->regs[3];
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} else {
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memset(childregs, 0, sizeof(struct pt_regs));
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childregs->pstate = PSR_MODE_EL1h;
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p->thread.cpu_context.x19 = stack_start;
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p->thread.cpu_context.x20 = stk_sz;
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}
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p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
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p->thread.cpu_context.sp = (unsigned long)childregs;
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ptrace_hw_copy_thread(p);
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return 0;
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}
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static void tls_thread_switch(struct task_struct *next)
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{
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unsigned long tpidr, tpidrro;
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asm("mrs %0, tpidr_el0" : "=r" (tpidr));
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*task_user_tls(current) = tpidr;
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tpidr = *task_user_tls(next);
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tpidrro = is_compat_thread(task_thread_info(next)) ?
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next->thread.tp_value : 0;
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asm(
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" msr tpidr_el0, %0\n"
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" msr tpidrro_el0, %1"
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: : "r" (tpidr), "r" (tpidrro));
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}
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/*
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* Thread switching.
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*/
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next)
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{
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struct task_struct *last;
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fpsimd_thread_switch(next);
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tls_thread_switch(next);
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hw_breakpoint_thread_switch(next);
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contextidr_thread_switch(next);
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/*
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* Complete any pending TLB or cache maintenance on this CPU in case
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* the thread migrates to a different CPU.
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*/
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dsb(ish);
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/* the actual thread switch */
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last = cpu_switch_to(prev, next);
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return last;
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}
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unsigned long get_wchan(struct task_struct *p)
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{
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struct stackframe frame;
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unsigned long stack_page;
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int count = 0;
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if (!p || p == current || p->state == TASK_RUNNING)
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return 0;
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frame.fp = thread_saved_fp(p);
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frame.sp = thread_saved_sp(p);
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frame.pc = thread_saved_pc(p);
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stack_page = (unsigned long)task_stack_page(p);
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do {
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if (frame.sp < stack_page ||
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frame.sp >= stack_page + THREAD_SIZE ||
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unwind_frame(&frame))
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return 0;
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if (!in_sched_functions(frame.pc))
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return frame.pc;
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} while (count ++ < 16);
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return 0;
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}
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unsigned long arch_align_stack(unsigned long sp)
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{
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if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
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sp -= get_random_int() & ~PAGE_MASK;
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return sp & ~0xf;
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}
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static unsigned long randomize_base(unsigned long base)
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{
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unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
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return randomize_range(base, range_end, 0) ? : base;
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}
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unsigned long arch_randomize_brk(struct mm_struct *mm)
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{
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return randomize_base(mm->brk);
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}
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