mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 19:35:15 +07:00
abe60a3a7a
Remove the usage of skeleton.dtsi in the remaining dts files. It was
deprecated since commit 9c0da3cc61 ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"). This will make adding a unit-address to
memory nodes easier.
The main tricky part to removing skeleton.dtsi is we could end up with
no /memory node at all when a bootloader depends on one being present. I
hacked up dtc to check for this condition.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
164 lines
3.6 KiB
Plaintext
164 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2014 MediaTek Inc.
|
|
* Author: Joe.C <yingjoe.chen@mediatek.com>
|
|
*
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "mediatek,mt8127";
|
|
interrupt-parent = <&sysirq>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "mediatek,mt81xx-tz-smp";
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x0>;
|
|
};
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x1>;
|
|
};
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x2>;
|
|
};
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
reg = <0x3>;
|
|
};
|
|
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
trustzone-bootinfo@80002000 {
|
|
compatible = "mediatek,trustzone-bootinfo";
|
|
reg = <0 0x80002000 0 0x1000>;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
system_clk: dummy13m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <13000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc_clk: dummy32k {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
uart_clk: dummy26m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <26000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <13000000>;
|
|
arm,cpu-registers-not-fw-configured;
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
timer: timer@10008000 {
|
|
compatible = "mediatek,mt8127-timer",
|
|
"mediatek,mt6577-timer";
|
|
reg = <0 0x10008000 0 0x80>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&system_clk>, <&rtc_clk>;
|
|
clock-names = "system-clk", "rtc-clk";
|
|
};
|
|
|
|
sysirq: interrupt-controller@10200100 {
|
|
compatible = "mediatek,mt8127-sysirq",
|
|
"mediatek,mt6577-sysirq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0 0x10200100 0 0x1c>;
|
|
};
|
|
|
|
gic: interrupt-controller@10211000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0 0x10211000 0 0x1000>,
|
|
<0 0x10212000 0 0x2000>,
|
|
<0 0x10214000 0 0x2000>,
|
|
<0 0x10216000 0 0x2000>;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x400>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x400>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@11004000 {
|
|
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
|
|
reg = <0 0x11004000 0 0x400>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@11005000 {
|
|
compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
|
|
reg = <0 0x11005000 0 0x400>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|