mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 19:55:05 +07:00
014e90ca44
commit137cd7100e"ARM: dts: Enable Gemini flash access" contained a bug by disabling the display controller, while the whole idea with the patch was to enable flash access AND the display controller, simultaneously. Fix it up. Fixes:137cd7100e("ARM: dts: Enable Gemini flash access") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
465 lines
11 KiB
Plaintext
465 lines
11 KiB
Plaintext
/*
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* Device Tree file for D-Link DIR-685 Xtreme N Storage Router
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*/
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/dts-v1/;
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#include "gemini.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "D-Link DIR-685 Xtreme N Storage Router";
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compatible = "dlink,dir-685", "cortina,gemini";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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/* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
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device_type = "memory";
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reg = <0x00000000 0x8000000>;
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};
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chosen {
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bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait";
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stdout-path = "uart0:19200n8";
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};
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gpio_keys {
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compatible = "gpio-keys";
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button-esc {
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debounce-interval = <100>;
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wakeup-source;
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linux,code = <KEY_ESC>;
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label = "reset";
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/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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};
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button-eject {
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debounce-interval = <100>;
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wakeup-source;
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linux,code = <KEY_EJECTCD>;
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label = "unmount";
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/* Collides with LPC LFRAME, UART RTS, SSP TXD */
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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};
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};
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vdisp: regulator {
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compatible = "regulator-fixed";
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regulator-name = "display-power";
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regulator-min-microvolt = <3600000>;
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regulator-max-microvolt = <3600000>;
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/* Collides with LCD E */
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gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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spi {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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/* Collides with IDE pins, that's cool (we do not use them) */
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gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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num-chipselects = <1>;
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panel: display@0 {
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compatible = "dlink,dir-685-panel", "ilitek,ili9322";
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reg = <0>;
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/* 50 ns min period = 20 MHz */
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spi-max-frequency = <20000000>;
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spi-cpol; /* Clock active low */
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vcc-supply = <&vdisp>;
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iovcc-supply = <&vdisp>;
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vci-supply = <&vdisp>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led-wps {
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label = "dir685:blue:WPS";
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/* Collides with ICE */
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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/*
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* These two LEDs are on the side of the device.
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* For electrical reasons, both LEDs cannot be active
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* at the same time so only blue or orange can be on at
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* one time. Enabling both makes the LED go dark.
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* The LEDs both sit inside the unmount button and the
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* label on the case says "unmount".
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*/
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led-blue-hd {
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label = "dir685:blue:HD";
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/* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
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gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "disk-read";
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};
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led-orange-hd {
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label = "dir685:orange:HD";
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/* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "disk-write";
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};
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};
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/*
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* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
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* Since the platform has no temperature sensor, this is controlled
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* from userspace by using the hard disks S.M.A.R.T. temperature
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* sensor. It is turned on when the temperature exceeds 46 degrees
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* and turned off when the temperatures goes below 41 degrees
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* (celsius).
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*/
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gpio-fan {
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compatible = "gpio-fan";
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/* Collides with IDE */
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gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = <0 0>, <10000 1>;
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#cooling-cells = <2>;
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};
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/*
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* The touchpad input is connected to a GPIO bit-banged
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* I2C bus.
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*/
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gpio-i2c {
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compatible = "i2c-gpio";
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/* Collides with ICE */
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sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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touchkeys@26 {
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compatible = "dlink,dir685-touchkeys";
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reg = <0x26>;
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interrupt-parent = <&gpio0>;
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/* Collides with NAND flash */
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interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
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switch {
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compatible = "realtek,rtl8366rb";
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/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
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mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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realtek,disable-leds;
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switch_intc: interrupt-controller {
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/* GPIO 15 provides the interrupt */
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interrupt-parent = <&gpio0>;
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interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&phy3>;
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};
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port@4 {
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reg = <4>;
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label = "wan";
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phy-handle = <&phy4>;
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};
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rtl8366rb_cpu_port: port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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compatible = "realtek,smi-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@0 {
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reg = <0>;
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interrupt-parent = <&switch_intc>;
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interrupts = <0>;
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};
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phy1: phy@1 {
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reg = <1>;
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interrupt-parent = <&switch_intc>;
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interrupts = <1>;
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};
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phy2: phy@2 {
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reg = <2>;
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interrupt-parent = <&switch_intc>;
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interrupts = <2>;
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};
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phy3: phy@3 {
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reg = <3>;
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interrupt-parent = <&switch_intc>;
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interrupts = <3>;
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};
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phy4: phy@4 {
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reg = <4>;
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interrupt-parent = <&switch_intc>;
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interrupts = <12>;
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};
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};
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};
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soc {
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flash@30000000 {
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/*
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* Flash access collides with the Chip Enable signal for
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* the display panel, that reuse the parallel flash Chip
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* Select 1 (CS1). We switch the pin control state so we
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* enable these pins for flash access only when we need
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* then, and when disabled they can be used for GPIO which
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* is what the display panel needs.
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*/
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status = "okay";
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pinctrl-names = "enabled", "disabled";
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pinctrl-0 = <&pflash_default_pins>;
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pinctrl-1 = <&pflash_disabled_pins>;
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/* 32MB of flash */
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reg = <0x30000000 0x02000000>;
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/*
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* This "RedBoot" is the Storlink derivative.
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*/
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partition@0 {
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label = "RedBoot";
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reg = <0x00000000 0x00040000>;
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read-only;
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};
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/*
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* This firmware image contains the kernel catenated
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* with the squashfs root filesystem. For some reason
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* this is called "upgrade" on the vendor system.
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*/
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partition@40000 {
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label = "upgrade";
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reg = <0x00040000 0x01f40000>;
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read-only;
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};
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/* RGDB, Residental Gateway Database? */
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partition@1f80000 {
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label = "rgdb";
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reg = <0x01f80000 0x00040000>;
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read-only;
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};
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/*
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* This partition contains MAC addresses for WAN,
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* WLAN and LAN, and the country code (for wireless
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* I guess).
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*/
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partition@1fc0000 {
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label = "nvram";
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reg = <0x01fc0000 0x00020000>;
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read-only;
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};
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partition@1fe0000 {
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label = "LangPack";
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reg = <0x01fe0000 0x00020000>;
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read-only;
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};
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};
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syscon: syscon@40000000 {
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pinctrl {
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/*
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* gpio0bgrp cover line 5, 6 used by TK I2C
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* gpio0bgrp cover line 7 used by WPS LED
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* gpio0cgrp cover line 8, 13 used by keys
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* and 11, 12 used by the HD LEDs
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* and line 14, 15 used by RTL8366
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* RESET and phy ready
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* gpio0egrp cover line 16 used by VDISP
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* gpio0fgrp cover line 17 used by TK IRQ
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* gpio0ggrp cover line 20 used by panel CS
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* gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
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*/
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gpio0_default_pins: pinctrl-gpio0 {
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mux {
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function = "gpio0";
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groups = "gpio0bgrp",
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"gpio0cgrp",
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"gpio0egrp",
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"gpio0fgrp",
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"gpio0hgrp";
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};
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};
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/*
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* gpio1bgrp cover line 5,8,7 used by panel SPI
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* also line 6 used by the fan
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*
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*/
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gpio1_default_pins: pinctrl-gpio1 {
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mux {
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function = "gpio1";
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groups = "gpio1bgrp";
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};
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};
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/*
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* These GPIO groups will be mapped in over some
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* of the flash pins when the flash is not in
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* active use.
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*/
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pflash_disabled_pins: pinctrl-pflash-disabled {
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mux {
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function = "gpio0";
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groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
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"gpio0kgrp";
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};
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};
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pinctrl-gmii {
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp";
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};
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conf0 {
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pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
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"Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
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"T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
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"U8 GMAC0 TXC", "V11 GMAC1 TXC",
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"W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
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"Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
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"T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
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"V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
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"Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
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"T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
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"U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
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"W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
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skew-delay = <7>;
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};
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/* Set up drive strength on GMAC0 to 16 mA */
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conf1 {
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groups = "gmii_gmac0_grp";
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drive-strength = <16>;
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};
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};
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};
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};
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sata: sata@46000000 {
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cortina,gemini-ata-muxmode = <0>;
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cortina,gemini-enable-sata-bridge;
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status = "okay";
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};
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gpio0: gpio@4d000000 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpio0_default_pins>;
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};
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gpio1: gpio@4e000000 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpio1_default_pins>;
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};
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pci@50000000 {
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status = "okay";
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map =
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<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
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<0x4800 0 0 2 &pci_intc 1>,
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<0x4800 0 0 3 &pci_intc 2>,
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<0x4800 0 0 4 &pci_intc 3>,
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<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
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<0x5000 0 0 2 &pci_intc 2>,
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<0x5000 0 0 3 &pci_intc 3>,
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<0x5000 0 0 4 &pci_intc 0>,
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<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
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<0x5800 0 0 2 &pci_intc 3>,
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<0x5800 0 0 3 &pci_intc 0>,
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<0x5800 0 0 4 &pci_intc 1>,
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<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
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<0x6000 0 0 2 &pci_intc 0>,
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<0x6000 0 0 3 &pci_intc 1>,
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<0x6000 0 0 4 &pci_intc 2>;
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};
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ethernet@60000000 {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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ethernet-port@1 {
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/* Not used in this platform */
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};
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};
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ata@63000000 {
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status = "okay";
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};
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display-controller@6a000000 {
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status = "okay";
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port@0 {
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reg = <0>;
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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usb@68000000 {
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status = "okay";
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};
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usb@69000000 {
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status = "okay";
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};
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};
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};
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