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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8635233ca5
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all current boards in <mach-generic/irq.h>. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Carsten Langgaard <carstenl@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_MALTAINT_H
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#define _MIPS_MALTAINT_H
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/*
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* Interrupts 0..15 are used for Malta ISA compatible interrupts
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*/
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#define MALTA_INT_BASE 0
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/* CPU interrupt offsets */
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#define MIPSCPU_INT_SW0 0
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#define MIPSCPU_INT_SW1 1
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
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#define MIPSCPU_INT_MB1 3
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#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
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#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
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#define MIPSCPU_INT_MB2 4
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#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
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#define MIPSCPU_INT_MB3 5
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#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
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#define MIPSCPU_INT_MB4 6
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#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
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/*
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* Interrupts 96..127 are used for Soc-it Classic interrupts
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*/
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#define MSC01C_INT_BASE 96
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/* SOC-it Classic interrupt offsets */
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#define MSC01C_INT_TMR 0
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#define MSC01C_INT_PCI 1
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/*
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* Interrupts 96..127 are used for Soc-it EIC interrupts
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*/
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#define MSC01E_INT_BASE 96
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/* SOC-it EIC interrupt offsets */
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#define MSC01E_INT_SW0 1
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#define MSC01E_INT_SW1 2
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#define MSC01E_INT_MB0 3
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#define MSC01E_INT_I8259A MSC01E_INT_MB0
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#define MSC01E_INT_MB1 4
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#define MSC01E_INT_SMI MSC01E_INT_MB1
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#define MSC01E_INT_MB2 5
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#define MSC01E_INT_MB3 6
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#define MSC01E_INT_COREHI MSC01E_INT_MB3
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#define MSC01E_INT_MB4 7
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#define MSC01E_INT_CORELO MSC01E_INT_MB4
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#define MSC01E_INT_TMR 8
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#define MSC01E_INT_PCI 9
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#define MSC01E_INT_PERFCTR 10
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#define MSC01E_INT_CPUCTR 11
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/* External Interrupts used for IPI */
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#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
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#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
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#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
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#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
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#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
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#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
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#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
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#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
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#endif /* !(_MIPS_MALTAINT_H) */
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