mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 23:46:40 +07:00
b8db6b886a
Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
/*
|
|
* AURORA shared L2 cache controller support
|
|
*
|
|
* Copyright (C) 2012 Marvell
|
|
*
|
|
* Yehuda Yitschak <yehuday@marvell.com>
|
|
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
|
|
#define __ASM_ARM_HARDWARE_AURORA_L2_H
|
|
|
|
#define AURORA_SYNC_REG 0x700
|
|
#define AURORA_RANGE_BASE_ADDR_REG 0x720
|
|
#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
|
|
#define AURORA_INVAL_RANGE_REG 0x774
|
|
#define AURORA_CLEAN_RANGE_REG 0x7b4
|
|
#define AURORA_FLUSH_RANGE_REG 0x7f4
|
|
|
|
#define AURORA_ACR_REPLACEMENT_OFFSET 27
|
|
#define AURORA_ACR_REPLACEMENT_MASK \
|
|
(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
|
|
#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \
|
|
(0 << AURORA_ACR_REPLACEMENT_OFFSET)
|
|
#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \
|
|
(1 << AURORA_ACR_REPLACEMENT_OFFSET)
|
|
#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
|
|
(3 << AURORA_ACR_REPLACEMENT_OFFSET)
|
|
|
|
#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
|
|
#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \
|
|
(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
|
|
#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \
|
|
(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
|
|
#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \
|
|
(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
|
|
#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
|
|
(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
|
|
|
|
#define MAX_RANGE_SIZE 1024
|
|
|
|
#define AURORA_WAY_SIZE_SHIFT 2
|
|
|
|
#define AURORA_CTRL_FW 0x100
|
|
|
|
/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
|
|
* the distinction between a number coming from hardware and a number
|
|
* coming from the device tree */
|
|
#define AURORA_CACHE_ID 0x100
|
|
|
|
#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
|