mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a3a8908fb0
Allow the timer core to change the smp affinity of the broadcast timer irq by setting CLOCK_EVT_FEAT_DYNIRQ flag. This reduces interrupt pressure and wakeups on CPU0 as well as vastly reducing the number of timer broadcast IPIs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
275 lines
6.7 KiB
C
275 lines
6.7 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/delay.h>
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#include <asm/mach/time.h>
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#include <asm/smp_twd.h>
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#define RTC_SECONDS 0x08
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#define RTC_SHADOW_SECONDS 0x0c
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#define RTC_MILLISECONDS 0x10
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#define TIMERUS_CNTR_1US 0x10
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#define TIMERUS_USEC_CFG 0x14
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#define TIMERUS_CNTR_FREEZE 0x4c
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#define TIMER1_BASE 0x0
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#define TIMER2_BASE 0x8
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#define TIMER3_BASE 0x50
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#define TIMER4_BASE 0x58
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#define TIMER_PTV 0x0
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#define TIMER_PCR 0x4
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static void __iomem *timer_reg_base;
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static void __iomem *rtc_base;
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static struct timespec64 persistent_ts;
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static u64 persistent_ms, last_persistent_ms;
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static struct delay_timer tegra_delay_timer;
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#define timer_writel(value, reg) \
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writel_relaxed(value, timer_reg_base + (reg))
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#define timer_readl(reg) \
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readl_relaxed(timer_reg_base + (reg))
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static int tegra_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 reg;
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reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
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timer_writel(reg, TIMER3_BASE + TIMER_PTV);
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return 0;
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}
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static inline void timer_shutdown(struct clock_event_device *evt)
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{
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timer_writel(0, TIMER3_BASE + TIMER_PTV);
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}
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static int tegra_timer_shutdown(struct clock_event_device *evt)
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{
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timer_shutdown(evt);
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return 0;
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}
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static int tegra_timer_set_periodic(struct clock_event_device *evt)
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{
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u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
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timer_shutdown(evt);
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timer_writel(reg, TIMER3_BASE + TIMER_PTV);
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return 0;
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}
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static struct clock_event_device tegra_clockevent = {
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.name = "timer0",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_DYNIRQ,
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.set_next_event = tegra_timer_set_next_event,
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.set_state_shutdown = tegra_timer_shutdown,
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.set_state_periodic = tegra_timer_set_periodic,
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.set_state_oneshot = tegra_timer_shutdown,
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.tick_resume = tegra_timer_shutdown,
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};
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static u64 notrace tegra_read_sched_clock(void)
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{
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return timer_readl(TIMERUS_CNTR_1US);
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}
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/*
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* tegra_rtc_read - Reads the Tegra RTC registers
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* Care must be taken that this funciton is not called while the
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* tegra_rtc driver could be executing to avoid race conditions
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* on the RTC shadow register
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*/
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static u64 tegra_rtc_read_ms(void)
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{
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u32 ms = readl(rtc_base + RTC_MILLISECONDS);
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u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
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return (u64)s * MSEC_PER_SEC + ms;
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}
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/*
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* tegra_read_persistent_clock64 - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec64.
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* Care must be taken that this funciton is not called while the
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* tegra_rtc driver could be executing to avoid race conditions
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* on the RTC shadow register
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*/
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static void tegra_read_persistent_clock64(struct timespec64 *ts)
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{
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u64 delta;
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last_persistent_ms = persistent_ms;
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persistent_ms = tegra_rtc_read_ms();
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delta = persistent_ms - last_persistent_ms;
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timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
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*ts = persistent_ts;
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}
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static unsigned long tegra_delay_timer_read_counter_long(void)
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{
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return readl(timer_reg_base + TIMERUS_CNTR_1US);
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}
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static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction tegra_timer_irq = {
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.name = "timer0",
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.flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
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.handler = tegra_timer_interrupt,
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.dev_id = &tegra_clockevent,
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};
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static void __init tegra20_init_timer(struct device_node *np)
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{
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struct clk *clk;
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unsigned long rate;
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int ret;
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timer_reg_base = of_iomap(np, 0);
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if (!timer_reg_base) {
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pr_err("Can't map timer registers\n");
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BUG();
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}
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tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
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if (tegra_timer_irq.irq <= 0) {
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pr_err("Failed to map timer IRQ\n");
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BUG();
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
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rate = 12000000;
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} else {
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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}
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switch (rate) {
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case 12000000:
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timer_writel(0x000b, TIMERUS_USEC_CFG);
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break;
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case 13000000:
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timer_writel(0x000c, TIMERUS_USEC_CFG);
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break;
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case 19200000:
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timer_writel(0x045f, TIMERUS_USEC_CFG);
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break;
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case 26000000:
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timer_writel(0x0019, TIMERUS_USEC_CFG);
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break;
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default:
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WARN(1, "Unknown clock rate");
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}
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sched_clock_register(tegra_read_sched_clock, 32, 1000000);
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if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
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"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
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pr_err("Failed to register clocksource\n");
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BUG();
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}
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tegra_delay_timer.read_current_timer =
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tegra_delay_timer_read_counter_long;
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tegra_delay_timer.freq = 1000000;
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register_current_timer_delay(&tegra_delay_timer);
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ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
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if (ret) {
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pr_err("Failed to register timer IRQ: %d\n", ret);
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BUG();
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}
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tegra_clockevent.cpumask = cpu_all_mask;
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tegra_clockevent.irq = tegra_timer_irq.irq;
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clockevents_config_and_register(&tegra_clockevent, 1000000,
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0x1, 0x1fffffff);
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}
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CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
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static void __init tegra20_init_rtc(struct device_node *np)
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{
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struct clk *clk;
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rtc_base = of_iomap(np, 0);
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if (!rtc_base) {
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pr_err("Can't map RTC registers");
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BUG();
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}
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/*
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* rtc registers are used by read_persistent_clock, keep the rtc clock
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* enabled
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*/
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk))
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pr_warn("Unable to get rtc-tegra clock\n");
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else
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clk_prepare_enable(clk);
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register_persistent_clock(NULL, tegra_read_persistent_clock64);
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}
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CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
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#ifdef CONFIG_PM
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static u32 usec_config;
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void tegra_timer_suspend(void)
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{
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usec_config = timer_readl(TIMERUS_USEC_CFG);
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}
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void tegra_timer_resume(void)
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{
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timer_writel(usec_config, TIMERUS_USEC_CFG);
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}
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#endif
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