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400e4b2091
'xsave.header::xstate_bv' is a misnomer - what does 'bv' stand for?
It probably comes from the 'XGETBV' instruction name, but I could
not find in the Intel documentation where that abbreviation comes
from. It could mean 'bit vector' - or something else?
But how about - instead of guessing about a weird name - we named
the field in an obvious and descriptive way that tells us exactly
what it does?
So rename it to 'xfeatures', which is a bitmask of the
xfeatures that are fpstate_active in that context structure.
Eyesore like:
fpu->state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
is now much more readable:
fpu->state->xsave.header.xfeatures |= XSTATE_FP;
Which form is not just infinitely more readable, but is also
shorter as well.
Reviewed-by: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
#ifndef _ASM_X86_USER_H
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#define _ASM_X86_USER_H
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#ifdef CONFIG_X86_32
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# include <asm/user_32.h>
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#else
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# include <asm/user_64.h>
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#endif
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#include <asm/types.h>
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struct user_ymmh_regs {
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/* 16 * 16 bytes for each YMMH-reg */
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__u32 ymmh_space[64];
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};
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struct user_xstate_header {
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__u64 xfeatures;
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__u64 reserved1[2];
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__u64 reserved2[5];
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};
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/*
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* The structure layout of user_xstateregs, used for exporting the
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* extended register state through ptrace and core-dump (NT_X86_XSTATE note)
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* interfaces will be same as the memory layout of xsave used by the processor
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* (except for the bytes 464..511, which can be used by the software) and hence
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* the size of this structure varies depending on the features supported by the
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* processor and OS. The size of the structure that users need to use can be
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* obtained by doing:
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* cpuid_count(0xd, 0, &eax, &ptrace_xstateregs_struct_size, &ecx, &edx);
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* i.e., cpuid.(eax=0xd,ecx=0).ebx will be the size that user (debuggers, etc.)
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* need to use.
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*
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* For now, only the first 8 bytes of the software usable bytes[464..471] will
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* be used and will be set to OS enabled xstate mask (which is same as the
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* 64bit mask returned by the xgetbv's xCR0). Users (analyzing core dump
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* remotely, etc.) can use this mask as well as the mask saved in the
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* xstate_hdr bytes and interpret what states the processor/OS supports
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* and what states are in modified/initialized conditions for the
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* particular process/thread.
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*
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* Also when the user modifies certain state FP/SSE/etc through the
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* ptrace interface, they must ensure that the header.xfeatures
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* bytes[512..519] of the memory layout are updated correspondingly.
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* i.e., for example when FP state is modified to a non-init state,
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* header.xfeatures's bit 0 must be set to '1', when SSE is modified to
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* non-init state, header.xfeatures's bit 1 must to be set to '1', etc.
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*/
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#define USER_XSTATE_FX_SW_WORDS 6
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#define USER_XSTATE_XCR0_WORD 0
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struct user_xstateregs {
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struct {
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__u64 fpx_space[58];
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__u64 xstate_fx_sw[USER_XSTATE_FX_SW_WORDS];
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} i387;
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struct user_xstate_header header;
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struct user_ymmh_regs ymmh;
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/* further processor state extensions go here */
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};
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#endif /* _ASM_X86_USER_H */
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