linux_dsm_epyc7002/drivers/clk/rockchip
Heiko Stübner 85fa0c7f8d clk: rockchip: add reset controller
All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset-
controller for SoC peripherals in their clock controller.
While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change
register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary.
To be compatible with both schemes the reset controller takes a flag to
decide which scheme to use, similar to the other HIWORD_MASK flags used in the
clock framework.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:07 -07:00
..
clk-pll.c clk: rockchip: add clock type for pll clocks and pll used on rk3066 2014-07-13 12:17:06 -07:00
clk-rockchip.c clk: rockchip: fix function type for CLK_OF_DECLARE 2014-05-20 14:25:22 -05:00
clk.c clk: rockchip: add clock type for pll clocks and pll used on rk3066 2014-07-13 12:17:06 -07:00
clk.h clk: rockchip: add reset controller 2014-07-13 12:17:07 -07:00
Makefile clk: rockchip: add reset controller 2014-07-13 12:17:07 -07:00
softrst.c clk: rockchip: add reset controller 2014-07-13 12:17:07 -07:00