mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 11:17:28 +07:00
62e59c4e69
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
187 lines
4.6 KiB
C
187 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car USB2.0 clock selector
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*
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* Copyright (C) 2017 Renesas Electronics Corp.
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*
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* Based on renesas-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#define USB20_CLKSET0 0x00
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#define CLKSET0_INTCLK_EN BIT(11)
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#define CLKSET0_PRIVATE BIT(0)
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#define CLKSET0_EXTAL_ONLY (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
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struct usb2_clock_sel_priv {
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void __iomem *base;
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struct clk_hw hw;
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bool extal;
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bool xtal;
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};
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#define to_priv(_hw) container_of(_hw, struct usb2_clock_sel_priv, hw)
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static void usb2_clock_sel_enable_extal_only(struct usb2_clock_sel_priv *priv)
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{
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u16 val = readw(priv->base + USB20_CLKSET0);
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pr_debug("%s: enter %d %d %x\n", __func__,
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priv->extal, priv->xtal, val);
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if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY)
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writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0);
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}
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static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
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{
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if (priv->extal && !priv->xtal)
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writew(CLKSET0_PRIVATE, priv->base + USB20_CLKSET0);
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}
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static int usb2_clock_sel_enable(struct clk_hw *hw)
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{
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usb2_clock_sel_enable_extal_only(to_priv(hw));
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return 0;
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}
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static void usb2_clock_sel_disable(struct clk_hw *hw)
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{
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usb2_clock_sel_disable_extal_only(to_priv(hw));
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}
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/*
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* This module seems a mux, but this driver assumes a gate because
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* ehci/ohci platform drivers don't support clk_set_parent() for now.
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* If this driver acts as a gate, ehci/ohci-platform drivers don't need
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* any modification.
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*/
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static const struct clk_ops usb2_clock_sel_clock_ops = {
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.enable = usb2_clock_sel_enable,
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.disable = usb2_clock_sel_disable,
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};
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static const struct of_device_id rcar_usb2_clock_sel_match[] = {
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{ .compatible = "renesas,rcar-gen3-usb2-clock-sel" },
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{ }
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};
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static int rcar_usb2_clock_sel_suspend(struct device *dev)
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{
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struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
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usb2_clock_sel_disable_extal_only(priv);
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pm_runtime_put(dev);
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return 0;
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}
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static int rcar_usb2_clock_sel_resume(struct device *dev)
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{
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struct usb2_clock_sel_priv *priv = dev_get_drvdata(dev);
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pm_runtime_get_sync(dev);
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usb2_clock_sel_enable_extal_only(priv);
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return 0;
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}
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static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct usb2_clock_sel_priv *priv = platform_get_drvdata(pdev);
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of_clk_del_provider(dev->of_node);
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clk_hw_unregister(&priv->hw);
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pm_runtime_put(dev);
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pm_runtime_disable(dev);
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return 0;
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}
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static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct usb2_clock_sel_priv *priv;
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struct resource *res;
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struct clk *clk;
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struct clk_init_data init;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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clk = devm_clk_get(dev, "usb_extal");
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if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
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priv->extal = !!clk_get_rate(clk);
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clk_disable_unprepare(clk);
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}
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clk = devm_clk_get(dev, "usb_xtal");
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if (!IS_ERR(clk) && !clk_prepare_enable(clk)) {
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priv->xtal = !!clk_get_rate(clk);
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clk_disable_unprepare(clk);
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}
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if (!priv->extal && !priv->xtal) {
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dev_err(dev, "This driver needs usb_extal or usb_xtal\n");
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return -ENOENT;
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}
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platform_set_drvdata(pdev, priv);
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dev_set_drvdata(dev, priv);
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init.name = "rcar_usb2_clock_sel";
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init.ops = &usb2_clock_sel_clock_ops;
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init.flags = 0;
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init.parent_names = NULL;
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init.num_parents = 0;
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priv->hw.init = &init;
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clk = clk_register(NULL, &priv->hw);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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return of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
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}
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static const struct dev_pm_ops rcar_usb2_clock_sel_pm_ops = {
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.suspend = rcar_usb2_clock_sel_suspend,
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.resume = rcar_usb2_clock_sel_resume,
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};
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static struct platform_driver rcar_usb2_clock_sel_driver = {
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.driver = {
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.name = "rcar-usb2-clock-sel",
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.of_match_table = rcar_usb2_clock_sel_match,
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.pm = &rcar_usb2_clock_sel_pm_ops,
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},
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.probe = rcar_usb2_clock_sel_probe,
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.remove = rcar_usb2_clock_sel_remove,
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};
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builtin_platform_driver(rcar_usb2_clock_sel_driver);
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MODULE_DESCRIPTION("Renesas R-Car USB2 clock selector Driver");
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MODULE_LICENSE("GPL v2");
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