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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e5fab2ec9c
This patch adds clocking support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller. The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. This mode needs a different clock generation scheme since the TMDS PHY clock must match the 10x ratio with the YUV420 pixel clock, but the video encoder must run at 2x the pixel clock. This patch adds the TMDS PHY clock value in all the video clock setup in order to better support these specific uses cases and switch to the Common Clock framework for clocks handling in the future. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jernej Škrabec <jernej.skrabec@siol.net> Link: https://patchwork.freedesktop.org/patch/msgid/20200304104052.17196-11-narmstrong@baylibre.com
296 lines
8.0 KiB
C
296 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/export.h>
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#include <linux/of_graph.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_device.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_print.h>
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#include "meson_registers.h"
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#include "meson_vclk.h"
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#include "meson_venc_cvbs.h"
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/* HHI VDAC Registers */
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
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struct meson_venc_cvbs {
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struct drm_encoder encoder;
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struct drm_connector connector;
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struct meson_drm *priv;
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};
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#define encoder_to_meson_venc_cvbs(x) \
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container_of(x, struct meson_venc_cvbs, encoder)
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#define connector_to_meson_venc_cvbs(x) \
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container_of(x, struct meson_venc_cvbs, connector)
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/* Supported Modes */
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struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT] = {
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{ /* PAL */
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.enci = &meson_cvbs_enci_pal,
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.mode = {
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DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
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720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
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DRM_MODE_FLAG_INTERLACE),
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.vrefresh = 50,
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.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
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},
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},
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{ /* NTSC */
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.enci = &meson_cvbs_enci_ntsc,
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.mode = {
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DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
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720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
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DRM_MODE_FLAG_INTERLACE),
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.vrefresh = 60,
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.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
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},
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},
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};
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static const struct meson_cvbs_mode *
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meson_cvbs_get_mode(const struct drm_display_mode *req_mode)
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{
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int i;
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for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
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struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
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if (drm_mode_match(req_mode, &meson_mode->mode,
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DRM_MODE_MATCH_TIMINGS |
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DRM_MODE_MATCH_CLOCK |
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DRM_MODE_MATCH_FLAGS |
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DRM_MODE_MATCH_3D_FLAGS))
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return meson_mode;
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}
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return NULL;
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}
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/* Connector */
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static void meson_cvbs_connector_destroy(struct drm_connector *connector)
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{
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drm_connector_cleanup(connector);
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}
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static enum drm_connector_status
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meson_cvbs_connector_detect(struct drm_connector *connector, bool force)
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{
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/* FIXME: Add load-detect or jack-detect if possible */
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return connector_status_connected;
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}
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static int meson_cvbs_connector_get_modes(struct drm_connector *connector)
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{
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struct drm_device *dev = connector->dev;
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struct drm_display_mode *mode;
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int i;
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for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
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struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
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mode = drm_mode_duplicate(dev, &meson_mode->mode);
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if (!mode) {
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DRM_ERROR("Failed to create a new display mode\n");
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return 0;
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}
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drm_mode_probed_add(connector, mode);
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}
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return i;
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}
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static int meson_cvbs_connector_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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/* Validate the modes added in get_modes */
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return MODE_OK;
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}
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static const struct drm_connector_funcs meson_cvbs_connector_funcs = {
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.detect = meson_cvbs_connector_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = meson_cvbs_connector_destroy,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const
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struct drm_connector_helper_funcs meson_cvbs_connector_helper_funcs = {
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.get_modes = meson_cvbs_connector_get_modes,
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.mode_valid = meson_cvbs_connector_mode_valid,
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};
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/* Encoder */
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static void meson_venc_cvbs_encoder_destroy(struct drm_encoder *encoder)
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{
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drm_encoder_cleanup(encoder);
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}
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static const struct drm_encoder_funcs meson_venc_cvbs_encoder_funcs = {
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.destroy = meson_venc_cvbs_encoder_destroy,
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};
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static int meson_venc_cvbs_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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if (meson_cvbs_get_mode(&crtc_state->mode))
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return 0;
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return -EINVAL;
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}
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static void meson_venc_cvbs_encoder_disable(struct drm_encoder *encoder)
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{
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struct meson_venc_cvbs *meson_venc_cvbs =
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encoder_to_meson_venc_cvbs(encoder);
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struct meson_drm *priv = meson_venc_cvbs->priv;
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/* Disable CVBS VDAC */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
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} else {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
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}
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}
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static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
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{
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struct meson_venc_cvbs *meson_venc_cvbs =
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encoder_to_meson_venc_cvbs(encoder);
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struct meson_drm *priv = meson_venc_cvbs->priv;
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/* VDAC0 source is not from ATV */
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writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
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priv->io_base + _REG(VENC_VDAC_DACSEL0));
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
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} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
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meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
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} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
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regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
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}
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}
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static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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const struct meson_cvbs_mode *meson_mode = meson_cvbs_get_mode(mode);
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struct meson_venc_cvbs *meson_venc_cvbs =
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encoder_to_meson_venc_cvbs(encoder);
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struct meson_drm *priv = meson_venc_cvbs->priv;
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if (meson_mode) {
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meson_venci_cvbs_mode_set(priv, meson_mode->enci);
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/* Setup 27MHz vclk2 for ENCI and VDAC */
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meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
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MESON_VCLK_CVBS, MESON_VCLK_CVBS,
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MESON_VCLK_CVBS, MESON_VCLK_CVBS,
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true);
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}
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}
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static const struct drm_encoder_helper_funcs
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meson_venc_cvbs_encoder_helper_funcs = {
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.atomic_check = meson_venc_cvbs_encoder_atomic_check,
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.disable = meson_venc_cvbs_encoder_disable,
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.enable = meson_venc_cvbs_encoder_enable,
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.mode_set = meson_venc_cvbs_encoder_mode_set,
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};
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static bool meson_venc_cvbs_connector_is_available(struct meson_drm *priv)
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{
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struct device_node *remote;
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remote = of_graph_get_remote_node(priv->dev->of_node, 0, 0);
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if (!remote)
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return false;
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of_node_put(remote);
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return true;
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}
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int meson_venc_cvbs_create(struct meson_drm *priv)
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{
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struct drm_device *drm = priv->drm;
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struct meson_venc_cvbs *meson_venc_cvbs;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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int ret;
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if (!meson_venc_cvbs_connector_is_available(priv)) {
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dev_info(drm->dev, "CVBS Output connector not available\n");
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return 0;
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}
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meson_venc_cvbs = devm_kzalloc(priv->dev, sizeof(*meson_venc_cvbs),
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GFP_KERNEL);
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if (!meson_venc_cvbs)
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return -ENOMEM;
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meson_venc_cvbs->priv = priv;
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encoder = &meson_venc_cvbs->encoder;
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connector = &meson_venc_cvbs->connector;
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/* Connector */
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drm_connector_helper_add(connector,
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&meson_cvbs_connector_helper_funcs);
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ret = drm_connector_init(drm, connector, &meson_cvbs_connector_funcs,
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DRM_MODE_CONNECTOR_Composite);
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if (ret) {
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dev_err(priv->dev, "Failed to init CVBS connector\n");
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return ret;
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}
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connector->interlace_allowed = 1;
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/* Encoder */
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drm_encoder_helper_add(encoder, &meson_venc_cvbs_encoder_helper_funcs);
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ret = drm_encoder_init(drm, encoder, &meson_venc_cvbs_encoder_funcs,
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DRM_MODE_ENCODER_TVDAC, "meson_venc_cvbs");
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if (ret) {
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dev_err(priv->dev, "Failed to init CVBS encoder\n");
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return ret;
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}
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encoder->possible_crtcs = BIT(0);
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drm_connector_attach_encoder(connector, encoder);
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return 0;
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}
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