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8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
149 lines
3.5 KiB
C
149 lines
3.5 KiB
C
/*
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* plat smp support for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include "common.h"
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static void __iomem *scu_base;
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static void __iomem *rsc_base;
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static DEFINE_SPINLOCK(boot_lock);
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static struct map_desc scu_io_desc __initdata = {
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init sirfsoc_map_scu(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = SIRFSOC_VA(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = (void __iomem *)SIRFSOC_VA(base);
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}
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static void sirfsoc_secondary_init(unsigned int cpu)
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{
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static struct of_device_id rsc_ids[] = {
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{ .compatible = "sirf,marco-rsc" },
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{},
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};
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static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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struct device_node *np;
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np = of_find_matching_node(NULL, rsc_ids);
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if (!np)
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return -ENODEV;
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rsc_base = of_iomap(np, 0);
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if (!rsc_base)
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return -ENOMEM;
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/*
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* write the address of secondary startup into the sram register
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* at offset 0x2C, then write the magic number 0x3CAF5D62 to the
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* RSC register at offset 0x28, which is what boot rom code is
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* waiting for. This would wake up the secondary core from WFE
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*/
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#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
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__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
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rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
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#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
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__raw_writel(0x3CAF5D62,
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rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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pen_release = cpu_logical_map(cpu);
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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/*
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* Send the secondary CPU SEV, thereby causing the boot monitor to read
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* the JUMPADDR and WAKEMAGIC, and branch to the address found there.
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*/
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dsb_sev();
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base);
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}
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struct smp_operations sirfsoc_smp_ops __initdata = {
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.smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
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.smp_secondary_init = sirfsoc_secondary_init,
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.smp_boot_secondary = sirfsoc_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = sirfsoc_cpu_die,
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#endif
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};
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