mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 05:46:47 +07:00
372 lines
7.9 KiB
C
372 lines
7.9 KiB
C
/*
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/imx-uart.h>
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#include "devices.h"
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static struct resource uart0[] = {
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{
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.start = UART1_BASE_ADDR,
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.end = UART1_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART1,
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.end = MXC_INT_UART1,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device0 = {
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.name = "imx-uart",
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.id = 0,
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.resource = uart0,
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.num_resources = ARRAY_SIZE(uart0),
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};
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static struct resource uart1[] = {
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{
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.start = UART2_BASE_ADDR,
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.end = UART2_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART2,
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.end = MXC_INT_UART2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device1 = {
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.name = "imx-uart",
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.id = 1,
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.resource = uart1,
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.num_resources = ARRAY_SIZE(uart1),
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};
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static struct resource uart2[] = {
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{
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.start = UART3_BASE_ADDR,
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.end = UART3_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART3,
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.end = MXC_INT_UART3,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device2 = {
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.name = "imx-uart",
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.id = 2,
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.resource = uart2,
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.num_resources = ARRAY_SIZE(uart2),
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};
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#ifdef CONFIG_ARCH_MX31
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static struct resource uart3[] = {
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{
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.start = UART4_BASE_ADDR,
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.end = UART4_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART4,
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.end = MXC_INT_UART4,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device3 = {
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.name = "imx-uart",
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.id = 3,
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.resource = uart3,
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.num_resources = ARRAY_SIZE(uart3),
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};
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static struct resource uart4[] = {
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{
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.start = UART5_BASE_ADDR,
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.end = UART5_BASE_ADDR + 0x0B5,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_UART5,
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.end = MXC_INT_UART5,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_uart_device4 = {
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.name = "imx-uart",
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.id = 4,
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.resource = uart4,
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.num_resources = ARRAY_SIZE(uart4),
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};
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#endif /* CONFIG_ARCH_MX31 */
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/* GPIO port description */
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static struct mxc_gpio_port imx_gpio_ports[] = {
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[0] = {
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.chip.label = "gpio-0",
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.base = IO_ADDRESS(GPIO1_BASE_ADDR),
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.irq = MXC_INT_GPIO1,
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.virtual_irq_start = MXC_GPIO_IRQ_START,
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},
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[1] = {
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.chip.label = "gpio-1",
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.base = IO_ADDRESS(GPIO2_BASE_ADDR),
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.irq = MXC_INT_GPIO2,
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.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
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},
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[2] = {
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.chip.label = "gpio-2",
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.base = IO_ADDRESS(GPIO3_BASE_ADDR),
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.irq = MXC_INT_GPIO3,
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.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
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}
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};
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int __init mxc_register_gpios(void)
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{
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return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
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}
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static struct resource mxc_w1_master_resources[] = {
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{
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.start = OWIRE_BASE_ADDR,
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.end = OWIRE_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mxc_w1_master_device = {
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.name = "mxc_w1",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
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.resource = mxc_w1_master_resources,
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};
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static struct resource mxc_nand_resources[] = {
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{
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.start = 0, /* runtime dependent */
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.end = 0,
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.flags = IORESOURCE_MEM
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}, {
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.start = MXC_INT_NANDFC,
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.end = MXC_INT_NANDFC,
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.flags = IORESOURCE_IRQ
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},
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};
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struct platform_device mxc_nand_device = {
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.name = "mxc_nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_nand_resources),
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.resource = mxc_nand_resources,
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};
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static struct resource mxc_i2c0_resources[] = {
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{
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.start = I2C_BASE_ADDR,
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.end = I2C_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MXC_INT_I2C,
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.end = MXC_INT_I2C,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device0 = {
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.name = "imx-i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
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.resource = mxc_i2c0_resources,
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};
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static struct resource mxc_i2c1_resources[] = {
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{
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.start = I2C2_BASE_ADDR,
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.end = I2C2_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MXC_INT_I2C2,
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.end = MXC_INT_I2C2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device1 = {
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.name = "imx-i2c",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
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.resource = mxc_i2c1_resources,
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};
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static struct resource mxc_i2c2_resources[] = {
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{
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.start = I2C3_BASE_ADDR,
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.end = I2C3_BASE_ADDR + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MXC_INT_I2C3,
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.end = MXC_INT_I2C3,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxc_i2c_device2 = {
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.name = "imx-i2c",
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.id = 2,
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.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
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.resource = mxc_i2c2_resources,
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};
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#ifdef CONFIG_ARCH_MX31
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static struct resource mxcsdhc0_resources[] = {
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{
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.start = MMC_SDHC1_BASE_ADDR,
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.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC1,
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.end = MXC_INT_MMC_SDHC1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource mxcsdhc1_resources[] = {
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{
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.start = MMC_SDHC2_BASE_ADDR,
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.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_MMC_SDHC2,
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.end = MXC_INT_MMC_SDHC2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mxcsdhc_device0 = {
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.name = "mxc-mmc",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
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.resource = mxcsdhc0_resources,
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};
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struct platform_device mxcsdhc_device1 = {
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.name = "mxc-mmc",
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.id = 1,
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.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
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.resource = mxcsdhc1_resources,
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};
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#endif /* CONFIG_ARCH_MX31 */
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/* i.MX31 Image Processing Unit */
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/* The resource order is important! */
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static struct resource mx3_ipu_rsrc[] = {
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{
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.start = IPU_CTRL_BASE_ADDR,
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.end = IPU_CTRL_BASE_ADDR + 0x5F,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IPU_CTRL_BASE_ADDR + 0x88,
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.end = IPU_CTRL_BASE_ADDR + 0xB3,
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.flags = IORESOURCE_MEM,
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}, {
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.start = MXC_INT_IPU_SYN,
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.end = MXC_INT_IPU_SYN,
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.flags = IORESOURCE_IRQ,
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}, {
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.start = MXC_INT_IPU_ERR,
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.end = MXC_INT_IPU_ERR,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device mx3_ipu = {
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.name = "ipu-core",
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.id = -1,
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.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
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.resource = mx3_ipu_rsrc,
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};
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static struct resource fb_resources[] = {
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{
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.start = IPU_CTRL_BASE_ADDR + 0xB4,
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.end = IPU_CTRL_BASE_ADDR + 0x1BF,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device mx3_fb = {
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.name = "mx3_sdc_fb",
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.id = -1,
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.num_resources = ARRAY_SIZE(fb_resources),
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.resource = fb_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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#ifdef CONFIG_ARCH_MX35
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static struct resource mxc_fec_resources[] = {
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{
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.start = MXC_FEC_BASE_ADDR,
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.end = MXC_FEC_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM
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}, {
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.start = MXC_INT_FEC,
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.end = MXC_INT_FEC,
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.flags = IORESOURCE_IRQ
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},
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};
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struct platform_device mxc_fec_device = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fec_resources),
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.resource = mxc_fec_resources,
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};
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#endif
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static int mx3_devices_init(void)
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{
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if (cpu_is_mx31()) {
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mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
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mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
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}
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if (cpu_is_mx35()) {
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mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
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mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
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}
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return 0;
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}
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subsys_initcall(mx3_devices_init);
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