mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 07:55:15 +07:00
9410113fc3
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200713123913.34205-1-grandmaster@al2klimov.de
244 lines
8.3 KiB
C
244 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Jyri Sarha <jsarha@ti.com>
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*/
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#ifndef __TIDSS_DISPC_REGS_H
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#define __TIDSS_DISPC_REGS_H
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enum dispc_common_regs {
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NOT_APPLICABLE_OFF = 0,
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DSS_REVISION_OFF,
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DSS_SYSCONFIG_OFF,
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DSS_SYSSTATUS_OFF,
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DISPC_IRQ_EOI_OFF,
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DISPC_IRQSTATUS_RAW_OFF,
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DISPC_IRQSTATUS_OFF,
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DISPC_IRQENABLE_SET_OFF,
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DISPC_IRQENABLE_CLR_OFF,
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DISPC_VID_IRQENABLE_OFF,
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DISPC_VID_IRQSTATUS_OFF,
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DISPC_VP_IRQENABLE_OFF,
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DISPC_VP_IRQSTATUS_OFF,
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WB_IRQENABLE_OFF,
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WB_IRQSTATUS_OFF,
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DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF,
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DISPC_GLOBAL_OUTPUT_ENABLE_OFF,
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DISPC_GLOBAL_BUFFER_OFF,
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DSS_CBA_CFG_OFF,
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DISPC_DBG_CONTROL_OFF,
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DISPC_DBG_STATUS_OFF,
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DISPC_CLKGATING_DISABLE_OFF,
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DISPC_SECURE_DISABLE_OFF,
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FBDC_REVISION_1_OFF,
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FBDC_REVISION_2_OFF,
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FBDC_REVISION_3_OFF,
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FBDC_REVISION_4_OFF,
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FBDC_REVISION_5_OFF,
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FBDC_REVISION_6_OFF,
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FBDC_COMMON_CONTROL_OFF,
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FBDC_CONSTANT_COLOR_0_OFF,
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FBDC_CONSTANT_COLOR_1_OFF,
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DISPC_CONNECTIONS_OFF,
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DISPC_MSS_VP1_OFF,
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DISPC_MSS_VP3_OFF,
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DISPC_COMMON_REG_TABLE_LEN,
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};
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/*
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* dispc_common_regmap should be defined as const u16 * and pointing
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* to a valid dss common register map for the platform, before the
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* macros bellow can be used.
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*/
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#define REG(r) (dispc_common_regmap[r ## _OFF])
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#define DSS_REVISION REG(DSS_REVISION)
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#define DSS_SYSCONFIG REG(DSS_SYSCONFIG)
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#define DSS_SYSSTATUS REG(DSS_SYSSTATUS)
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#define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI)
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#define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW)
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#define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS)
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#define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET)
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#define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR)
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#define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4)
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#define DISPC_VID_IRQSTATUS(n) (REG(DISPC_VID_IRQSTATUS) + (n) * 4)
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#define DISPC_VP_IRQENABLE(n) (REG(DISPC_VP_IRQENABLE) + (n) * 4)
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#define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4)
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#define WB_IRQENABLE REG(WB_IRQENABLE)
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#define WB_IRQSTATUS REG(WB_IRQSTATUS)
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#define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE)
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#define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE)
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#define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER)
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#define DSS_CBA_CFG REG(DSS_CBA_CFG)
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#define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL)
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#define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS)
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#define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE)
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#define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE)
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#define FBDC_REVISION_1 REG(FBDC_REVISION_1)
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#define FBDC_REVISION_2 REG(FBDC_REVISION_2)
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#define FBDC_REVISION_3 REG(FBDC_REVISION_3)
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#define FBDC_REVISION_4 REG(FBDC_REVISION_4)
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#define FBDC_REVISION_5 REG(FBDC_REVISION_5)
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#define FBDC_REVISION_6 REG(FBDC_REVISION_6)
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#define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL)
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#define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0)
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#define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1)
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#define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS)
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#define DISPC_MSS_VP1 REG(DISPC_MSS_VP1)
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#define DISPC_MSS_VP3 REG(DISPC_MSS_VP3)
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/* VID */
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#define DISPC_VID_ACCUH_0 0x0
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#define DISPC_VID_ACCUH_1 0x4
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#define DISPC_VID_ACCUH2_0 0x8
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#define DISPC_VID_ACCUH2_1 0xc
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#define DISPC_VID_ACCUV_0 0x10
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#define DISPC_VID_ACCUV_1 0x14
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#define DISPC_VID_ACCUV2_0 0x18
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#define DISPC_VID_ACCUV2_1 0x1c
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#define DISPC_VID_ATTRIBUTES 0x20
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#define DISPC_VID_ATTRIBUTES2 0x24
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#define DISPC_VID_BA_0 0x28
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#define DISPC_VID_BA_1 0x2c
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#define DISPC_VID_BA_UV_0 0x30
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#define DISPC_VID_BA_UV_1 0x34
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#define DISPC_VID_BUF_SIZE_STATUS 0x38
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#define DISPC_VID_BUF_THRESHOLD 0x3c
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#define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4)
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#define DISPC_VID_FIRH 0x5c
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#define DISPC_VID_FIRH2 0x60
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#define DISPC_VID_FIRV 0x64
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#define DISPC_VID_FIRV2 0x68
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#define DISPC_VID_FIR_COEFS_H0 0x6c
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#define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_H0_C 0x90
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#define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_H12 0xb4
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#define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_H12_C 0xf4
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#define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_V0 0x134
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#define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_V0_C 0x158
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#define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_V12 0x17c
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#define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4)
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#define DISPC_VID_FIR_COEFS_V12_C 0x1bc
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#define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4)
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#define DISPC_VID_GLOBAL_ALPHA 0x1fc
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#define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */
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#define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */
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#define DISPC_VID_MFLAG_THRESHOLD 0x208
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#define DISPC_VID_PICTURE_SIZE 0x20c
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#define DISPC_VID_PIXEL_INC 0x210
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#define DISPC_VID_K2G_POSITION 0x214 /* K2G */
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#define DISPC_VID_PRELOAD 0x218
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#define DISPC_VID_ROW_INC 0x21c
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#define DISPC_VID_SIZE 0x220
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#define DISPC_VID_BA_EXT_0 0x22c
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#define DISPC_VID_BA_EXT_1 0x230
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#define DISPC_VID_BA_UV_EXT_0 0x234
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#define DISPC_VID_BA_UV_EXT_1 0x238
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#define DISPC_VID_CSC_COEF7 0x23c
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#define DISPC_VID_ROW_INC_UV 0x248
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#define DISPC_VID_CLUT 0x260
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#define DISPC_VID_SAFETY_ATTRIBUTES 0x2a0
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#define DISPC_VID_SAFETY_CAPT_SIGNATURE 0x2a4
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#define DISPC_VID_SAFETY_POSITION 0x2a8
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#define DISPC_VID_SAFETY_REF_SIGNATURE 0x2ac
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#define DISPC_VID_SAFETY_SIZE 0x2b0
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#define DISPC_VID_SAFETY_LFSR_SEED 0x2b4
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#define DISPC_VID_LUMAKEY 0x2b8
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#define DISPC_VID_DMA_BUFSIZE 0x2bc /* J721E */
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/* OVR */
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#define DISPC_OVR_CONFIG 0x0
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#define DISPC_OVR_VIRTVP 0x4 /* J721E */
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#define DISPC_OVR_DEFAULT_COLOR 0x8
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#define DISPC_OVR_DEFAULT_COLOR2 0xc
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#define DISPC_OVR_TRANS_COLOR_MAX 0x10
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#define DISPC_OVR_TRANS_COLOR_MAX2 0x14
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#define DISPC_OVR_TRANS_COLOR_MIN 0x18
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#define DISPC_OVR_TRANS_COLOR_MIN2 0x1c
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#define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4)
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#define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */
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/* VP */
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#define DISPC_VP_CONFIG 0x0
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#define DISPC_VP_CONTROL 0x4
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#define DISPC_VP_CSC_COEF0 0x8
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#define DISPC_VP_CSC_COEF1 0xc
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#define DISPC_VP_CSC_COEF2 0x10
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#define DISPC_VP_DATA_CYCLE_0 0x14
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#define DISPC_VP_DATA_CYCLE_1 0x18
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#define DISPC_VP_K2G_GAMMA_TABLE 0x20 /* K2G */
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#define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */
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#define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */
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#define DISPC_VP_DATA_CYCLE_2 0x1c
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#define DISPC_VP_LINE_NUMBER 0x44
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#define DISPC_VP_POL_FREQ 0x4c
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#define DISPC_VP_SIZE_SCREEN 0x50
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#define DISPC_VP_TIMING_H 0x54
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#define DISPC_VP_TIMING_V 0x58
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#define DISPC_VP_CSC_COEF3 0x5c
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#define DISPC_VP_CSC_COEF4 0x60
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#define DISPC_VP_CSC_COEF5 0x64
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#define DISPC_VP_CSC_COEF6 0x68
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#define DISPC_VP_CSC_COEF7 0x6c
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#define DISPC_VP_SAFETY_ATTRIBUTES_0 0x70
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#define DISPC_VP_SAFETY_ATTRIBUTES_1 0x74
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#define DISPC_VP_SAFETY_ATTRIBUTES_2 0x78
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#define DISPC_VP_SAFETY_ATTRIBUTES_3 0x7c
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#define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 0x90
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#define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 0x94
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#define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 0x98
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#define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 0x9c
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#define DISPC_VP_SAFETY_POSITION_0 0xb0
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#define DISPC_VP_SAFETY_POSITION_1 0xb4
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#define DISPC_VP_SAFETY_POSITION_2 0xb8
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#define DISPC_VP_SAFETY_POSITION_3 0xbc
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#define DISPC_VP_SAFETY_REF_SIGNATURE_0 0xd0
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#define DISPC_VP_SAFETY_REF_SIGNATURE_1 0xd4
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#define DISPC_VP_SAFETY_REF_SIGNATURE_2 0xd8
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#define DISPC_VP_SAFETY_REF_SIGNATURE_3 0xdc
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#define DISPC_VP_SAFETY_SIZE_0 0xf0
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#define DISPC_VP_SAFETY_SIZE_1 0xf4
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#define DISPC_VP_SAFETY_SIZE_2 0xf8
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#define DISPC_VP_SAFETY_SIZE_3 0xfc
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#define DISPC_VP_SAFETY_LFSR_SEED 0x110
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#define DISPC_VP_GAMMA_TABLE 0x120
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#define DISPC_VP_DSS_OLDI_CFG 0x160
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#define DISPC_VP_DSS_OLDI_STATUS 0x164
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#define DISPC_VP_DSS_OLDI_LB 0x168
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#define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */
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#define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */
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#define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */
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/*
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* OLDI IO_CTRL register offsets. On AM654 the registers are found
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* from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from
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* CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL
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* register range.
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*/
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#define OLDI_DAT0_IO_CTRL 0x00
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#define OLDI_DAT1_IO_CTRL 0x04
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#define OLDI_DAT2_IO_CTRL 0x08
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#define OLDI_DAT3_IO_CTRL 0x0C
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#define OLDI_CLK_IO_CTRL 0x10
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#define OLDI_PWRDN_TX BIT(8)
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#endif /* __TIDSS_DISPC_REGS_H */
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