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735302665c
Commit1c3c5eab17("sched/core: Enable might_sleep() and smp_processor_id() checks early") enables checks for might_sleep() and smp_processor_id() being used in preemptible code earlier in the boot than before. This results in a new BUG from pcibios_set_cache_line_size(). BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1 caller is pcibios_set_cache_line_size+0x10/0x70 CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-00007-g3ce3e4ba4275 #615 Stack: 0000000000000000 ffffffff81189694 0000000000000000 ffffffff81822318 000000000000004e 0000000000000001 800000000e20bd08 20c49ba5e3540000 0000000000000000 0000000000000000 ffffffff818d0000 0000000000000000 0000000000000000 ffffffff81189328 ffffffff818ce692 0000000000000000 0000000000000000 ffffffff81189bc8 ffffffff818d0000 0000000000000000 ffffffff81828907 ffffffff81769970 800000020ec78d80 ffffffff818c7b48 0000000000000001 0000000000000001 ffffffff818652b0 ffffffff81896268 ffffffff818c0000 800000020ec7fb40 800000020ec7fc58 ffffffff81684cac 0000000000000000 ffffffff8118ab50 0000000000000030 ffffffff81769970 0000000000000001 ffffffff81122a58 0000000000000000 0000000000000000 ... Call Trace: [<ffffffff81122a58>] show_stack+0x90/0xb0 [<ffffffff81684cac>] dump_stack+0xac/0xf0 [<ffffffff813f7050>] check_preemption_disabled+0x120/0x128 [<ffffffff818855e8>] pcibios_set_cache_line_size+0x10/0x70 [<ffffffff81100578>] do_one_initcall+0x48/0x140 [<ffffffff81865dc4>] kernel_init_freeable+0x194/0x24c [<ffffffff8169c534>] kernel_init+0x14/0x118 [<ffffffff8111ca84>] ret_from_kernel_thread+0x14/0x1c Fix this by using the cpu_*cache_line_size() macros instead. These macros are the "proper" way to determine the CPU cache sizes. This makes use of the newly added cpu_tcache_line_size. Fixes:1c3c5eab17("sched/core: Enable might_sleep() and smp_processor_id() checks early") Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Suggested-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <asm/cpu-info.h>
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unsigned long PCIBIOS_MIN_IO;
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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unsigned long PCIBIOS_MIN_MEM;
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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static int __init pcibios_set_cache_line_size(void)
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{
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the highest level in the
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* cache hierarchy.
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*/
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lsize = cpu_dcache_line_size();
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lsize = cpu_scache_line_size() ? : lsize;
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lsize = cpu_tcache_line_size() ? : lsize;
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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return 0;
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}
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arch_initcall(pcibios_set_cache_line_size);
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void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc, resource_size_t *start,
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resource_size_t *end)
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{
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phys_addr_t size = resource_size(rsrc);
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*start = fixup_bigphys_addr(rsrc->start, size);
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*end = rsrc->start + size;
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}
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